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IEEE Transactions on Magnetics

High speed non-latching SQUID binary ripple counter

Arnold H. Silver, R. Phillips, Robert D. Sandell

Published Mar 1, 1985• 29 citations
Publisher

Abstract

High speed, single flux quantum (SFQ) binary scalers are important components in superconducting analog-to-digital converters (ADC). This paper reviews the concept for a SQUID ADC and the design of an SFQ binary ripple counter, and reports the simulation of key components, and fabrication and performance of non-latching SQUID scalers and SFQ binary ripple counters. The SQUIDs were fabricated with Nb/Nb2O5/PbIn junctions and interconnected by monolithic-superconducting transmission lines and isolation resistors. Each SQUID functioned as a bistable flip-flop with the input connected to the center of the device and the output across one junction. All junctions were critically damped to optimize the pulse response. Operation was verified by observing the do I-V curves of successive SQUIDs driven by a cw pulse train generated on the same chip. Each SQUID exhibited constant-voltage current steps at 1/2 the voltage of the preceding device as expected from the Josephson voltage-to-frequency relation. Steps were observed only for the same voltage polarity of successive devices and for proper phase bias of the SQUID. Binary frequency division was recorded up to 40GHz for devices designed to operate to 28GHz.

DOI
10.1109/tmag.1985.1063723

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High speed, single flux quantum (SFQ) binary scalers are important components in superconducting analog-to-digital converters (ADC). This paper reviews the concept for a SQUID ADC and the design of an SFQ binary ripple counter, and reports the simulation of key components, and fabrication and performance of non-latching SQUID scalers and SFQ binary ripple counters. The SQUIDs were fabricated with Nb/Nb2O5/PbIn junctions and interconnected by monolithic-superconducting transmission lines and isolation resistors. Each SQUID functioned as a bistable flip-flop with the input connected to the center of the device and the output across one junction. All junctions were critically damped to optimize the pulse response. Operation was verified by observing the do I-V curves of successive SQUIDs driven by a cw pulse train generated on the same chip. Each SQUID exhibited constant-voltage current steps at 1/2 the voltage of the preceding device as expected from the Josephson voltage-to-frequency relation. Steps were observed only for the same voltage polarity of successive devices and for proper phase bias of the SQUID. Binary frequency division was recorded up to 40GHz for devices designed to operate to 28GHz.
Digital Josephson circuits that do not latch into the voltage state provide an opportunity for high-speed serial processing. These fast logic gates must ultimately generate and record small fast pulses generated by single fluxoid events. This is demonstrated in a concept for a high-speed analog-to-digital (A/D) converter. Low β-value unlatched SQUID's are used throughout for ultimate speed, sensitivity, and simplicity. The analog signal is quantized by a single-junction SQUID and converted into a pulse train resulting from fluxoid transitions. These are counted in a chain of bistable two-junction SQUID's which successively scale the pulse train by a factor 2. These SQUID's perform both logic and memory functions at the single fluxoid level. The bit count stored in the array is gated out each sampling interval to provide the digitized signal. The performance of this device has been simulated and criteria established for the unlatched SQUID design. These include dimensionality, impedance, damping, intra- and inter-SQUID delays and β factor. Large analog dynamic range is available with the high intrinsic linearity of the SQUID quantizer and a long chain of scalers.
Single-flux quantum devices are used in superconductive analog-to-digital converters (ADCs), shift registers, and memory cells. They have been proposed for logic applications. The authors report the performance of high-speed superconducting, single-flux quantum (SFQ) ripple counters. Both memory and logic functions of the counter are investigated. Errors in logic operation produce bit error rates (BERs) as low as 0.22 errors per million binary operations, measured while counting 100-MHz pseudorandom input pulses. Errors in memory function do not occur on the time scale of the measurements. The BER is shown to be nearly independent of input bit rate and pattern, but strongly dependent on the counter cell operating point.< >
We have characterized Nb analog to digital converters using a resistor-coupled SFQ flip flop counter and a latching destructive readout (DRO). The counter used SFQ buffers between bits to provide isolation during destructive readout. We have measured parallel readout at sample rates up to 125 MSPS. We have also successfully operated an ADC which has Josephson junction regulated flip flop gate and readout bias busses. Using a self-resetting gate (SRG) at the carry out of the counter, we have measured the bit error rates (BER) of the counters. A two junction SQUID quantizer, biased in the voltage state, was used to produce correlated SFQ pulses at each junction. The SRG outputs of two 10 bit counters connected to the two quantizer outputs were compared. We measured a BER of /spl sim/5/spl times/10/sup -11/ with the quantizer operating at 19 GHz. We believe the principle error source is the latching SRG.
We have fabricated and measured high T/sub c/ superconductor single flux quantum 1-bit flux-counting analog-to-digital converters (ADCs). The ADCs were made with a multilayer all-epitaxial process which incorporates 10 edge SNS (superconductor-normal-superconductor) or step-edge grain boundary (SEGB) Josephson junctions with a YBa/sub 2/Cu/sub 3/O/sub 7-/spl delta// groundplane. The ADC consists of a quantizer connected to a Toggle flip-flop through a buffer-like stage. Direct readout of the flux state of the T flip-flop was made with a Read SQUID inductively coupled through a hole in the groundplane. The circuits were operated at 65 K and low speeds. The SNS circuits outperformed the SEGB circuits because of their higher readout voltages and tighter critical current spreads.
We have developed and demonstrated a digital to analog converter DAC which uses an SFQ counter to precisely divide an input reference oscillator to produce a set of binary frequencies/voltages. The binary input gates the output SFQ pulses of the counter flip flops to a passive summing network, producing an analog output current. The DAC is asynchronous (no clock to reset latching circuits), low power, and requires only N equal matched resistors. We have built and tested a 4-bit Nb DAC with data clocking rates up to 1 GHz. Using the DAC we have generated arbitrary wave forms including ramps and sine waves. By measuring the harmonic content of sine wave outputs, we deduce values for the DAC linearity.
A Josephson binary counter using single-flux quanta transitions of DC SQUIDs (superconducting quantum interference devices) has been fabricated using an eight-level NbN-based process. High-speed binary division has been demonstrated at 4.2 K, with single-cell counting observed at 60 GHz using the Josephson voltage-to-frequency relationship. Count rate was primarily limited by conservative process and design rules. The counter was designed for operation at 4.2 K. At 8-10 K, the beta /sub L/ of the SQUIDs would not allow operation, though the junction characteristics were good.>