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IEEE Transactions on Applied Superconductivity

An SFQ digital to analog converter

Robert D. Sandell, Bruce J. Dalrymple, A.D. Smith

Published Jun 1, 1997• 3 citations
Publisher

Abstract

We have developed and demonstrated a digital to analog converter DAC which uses an SFQ counter to precisely divide an input reference oscillator to produce a set of binary frequencies/voltages. The binary input gates the output SFQ pulses of the counter flip flops to a passive summing network, producing an analog output current. The DAC is asynchronous (no clock to reset latching circuits), low power, and requires only N equal matched resistors. We have built and tested a 4-bit Nb DAC with data clocking rates up to 1 GHz. Using the DAC we have generated arbitrary wave forms including ramps and sine waves. By measuring the harmonic content of sine wave outputs, we deduce values for the DAC linearity.

DOI
10.1109/77.621739

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We have developed and demonstrated a digital to analog converter DAC which uses an SFQ counter to precisely divide an input reference oscillator to produce a set of binary frequencies/voltages. The binary input gates the output SFQ pulses of the counter flip flops to a passive summing network, producing an analog output current. The DAC is asynchronous (no clock to reset latching circuits), low power, and requires only N equal matched resistors. We have built and tested a 4-bit Nb DAC with data clocking rates up to 1 GHz. Using the DAC we have generated arbitrary wave forms including ramps and sine waves. By measuring the harmonic content of sine wave outputs, we deduce values for the DAC linearity.
We have characterized Nb analog to digital converters using a resistor-coupled SFQ flip flop counter and a latching destructive readout (DRO). The counter used SFQ buffers between bits to provide isolation during destructive readout. We have measured parallel readout at sample rates up to 125 MSPS. We have also successfully operated an ADC which has Josephson junction regulated flip flop gate and readout bias busses. Using a self-resetting gate (SRG) at the carry out of the counter, we have measured the bit error rates (BER) of the counters. A two junction SQUID quantizer, biased in the voltage state, was used to produce correlated SFQ pulses at each junction. The SRG outputs of two 10 bit counters connected to the two quantizer outputs were compared. We measured a BER of /spl sim/5/spl times/10/sup -11/ with the quantizer operating at 19 GHz. We believe the principle error source is the latching SRG.
Abstract One of the unique applications of single-flux-quantum (SFQ) circuitry is a digital-to-analog converter (DAC) of which the output voltage is defined by the Josephson effect. Recently, we have designed and operated rapid single-flux-quantum (RSFQ) DACs with frequency modulation of SFQ pulse sequences. In this paper, we report our design and test results of a 4-bit RSFQ-DAC based on the configuration of the “sum of selected bits sequence (Σ-SBS)”. By adjusting the timing margins, in addition to the fabrication using the Nb integration process with the critical current density as high as 10 kA/cm2, the maximum output voltage up to 260 μV was demonstrated.
The design and operation of a 9 bit superconductive single‐flux‐quantum (SFQ) digital‐to‐analogue converter (DAC) are presented. The DAC comprises a 9 bit variable SFQ pulse number multiplier and a 100‐fold voltage multiplier. An SFQ pulse‐frequency modulation technique is employed for coding the analogue output voltage. The DAC is fabricated using an Nb Josephson integration technology. Its output voltage waveform, the amplitude of which is up to 2.54 m V pp , is controlled by digital input signals from a room‐temperature data generator.
Digital to analog converters based on the Josephson effect are promising for voltage standards, because they produce voltage steps with ultimate precision and stability. In this paper, we describe a project to develop a Josephson D/A converter designed for synthesizing a sinusoidal waveform with metrological accuracy. The D/A converter is based on RSFQ (Rapid Single Flux Quantum) logic circuits, and consists of a frequency multiplier (FM), a pulse distributor (PD), and a number of voltage multipliers (VMs). Each VM circuit, corresponding to the n-th bit digital code, multiplies the number of SFQ pulses by a factor of 2/sup n/. By gating the input SFQ pulses from the FM to the VMs using the PD circuits, a programmable output voltage is obtained. Possible sources of uncertainties in the measurement of the rms value of the synthesized sine wave are discussed.
A new A/D converter which includes a comparator, and a reversible binary counter with DC outputs has been designed, fabricated, and tested. The comparator generates two trains of the single-flux-quantum (SFQ) pulses in response to increasing or decreasing input signal. The pulses are transferred through SFQ transmission lines to the adding and diminishing inputs of a reversible counter. The reversible counter has been realized by supplementing the usual counter with the SFQ transmission lines, splitters; and confluence elements for sending diminished pulses directly to each bit. Nondestructive read-out of the counter contents is carried out by SFQ/DC converters connected to each counter bit. The integrated circuit is fabricated using 5- mu m Nb-AlO/sub x/-Nb Josephson junction technology with a critical current density about 500 A/cm/sup 2/. External Mo shunts of the junctions provide the value of beta /sub c/<or=1 and I/sub c/R approximately=300 mu V. The A/D conversion is studied for low-frequency signals with an external clock. High-frequency performance of the reversible counter has been tested.
Recently we designed and successfully tested a prototype of a superconducting digital-to-analog converter (DAC) based on processing single flux quantum (SFQ) pulses. Two unique features make the device very attractive for metrology applications: (i) The generation of output voltage is based on the fundamentally accurate Josephson frequency-to-voltage relationship. (ii) The device does not require any external signals with frequencies higher than 100 MHz. It is expected that the DAC will be used as a key component of novel standards and calibrators of ac voltage with frequency up to 1 MHz. The implemented prototype has low magnitude of output voltage (about 10 mV) which is far lower than the 1 to 10 V target magnitude.