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IEEE Transactions on Applied Superconductivity

Counting SFQ analog to digital converter results

Robert D. Sandell, D.J. Durand, Bruce J. Dalrymple, T.H. Pham

Published Jun 1, 1997• 0 citations
Publisher

Abstract

We have characterized Nb analog to digital converters using a resistor-coupled SFQ flip flop counter and a latching destructive readout (DRO). The counter used SFQ buffers between bits to provide isolation during destructive readout. We have measured parallel readout at sample rates up to 125 MSPS. We have also successfully operated an ADC which has Josephson junction regulated flip flop gate and readout bias busses. Using a self-resetting gate (SRG) at the carry out of the counter, we have measured the bit error rates (BER) of the counters. A two junction SQUID quantizer, biased in the voltage state, was used to produce correlated SFQ pulses at each junction. The SRG outputs of two 10 bit counters connected to the two quantizer outputs were compared. We measured a BER of /spl sim/5/spl times/10/sup -11/ with the quantizer operating at 19 GHz. We believe the principle error source is the latching SRG.

DOI
10.1109/77.622060

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We have characterized Nb analog to digital converters using a resistor-coupled SFQ flip flop counter and a latching destructive readout (DRO). The counter used SFQ buffers between bits to provide isolation during destructive readout. We have measured parallel readout at sample rates up to 125 MSPS. We have also successfully operated an ADC which has Josephson junction regulated flip flop gate and readout bias busses. Using a self-resetting gate (SRG) at the carry out of the counter, we have measured the bit error rates (BER) of the counters. A two junction SQUID quantizer, biased in the voltage state, was used to produce correlated SFQ pulses at each junction. The SRG outputs of two 10 bit counters connected to the two quantizer outputs were compared. We measured a BER of /spl sim/5/spl times/10/sup -11/ with the quantizer operating at 19 GHz. We believe the principle error source is the latching SRG.
We have developed and demonstrated a digital to analog converter DAC which uses an SFQ counter to precisely divide an input reference oscillator to produce a set of binary frequencies/voltages. The binary input gates the output SFQ pulses of the counter flip flops to a passive summing network, producing an analog output current. The DAC is asynchronous (no clock to reset latching circuits), low power, and requires only N equal matched resistors. We have built and tested a 4-bit Nb DAC with data clocking rates up to 1 GHz. Using the DAC we have generated arbitrary wave forms including ramps and sine waves. By measuring the harmonic content of sine wave outputs, we deduce values for the DAC linearity.
High speed, single flux quantum (SFQ) binary scalers are important components in superconducting analog-to-digital converters (ADC). This paper reviews the concept for a SQUID ADC and the design of an SFQ binary ripple counter, and reports the simulation of key components, and fabrication and performance of non-latching SQUID scalers and SFQ binary ripple counters. The SQUIDs were fabricated with Nb/Nb2O5/PbIn junctions and interconnected by monolithic-superconducting transmission lines and isolation resistors. Each SQUID functioned as a bistable flip-flop with the input connected to the center of the device and the output across one junction. All junctions were critically damped to optimize the pulse response. Operation was verified by observing the do I-V curves of successive SQUIDs driven by a cw pulse train generated on the same chip. Each SQUID exhibited constant-voltage current steps at 1/2 the voltage of the preceding device as expected from the Josephson voltage-to-frequency relation. Steps were observed only for the same voltage polarity of successive devices and for proper phase bias of the SQUID. Binary frequency division was recorded up to 40GHz for devices designed to operate to 28GHz.
We have fabricated and measured high T/sub c/ superconductor single flux quantum 1-bit flux-counting analog-to-digital converters (ADCs). The ADCs were made with a multilayer all-epitaxial process which incorporates 10 edge SNS (superconductor-normal-superconductor) or step-edge grain boundary (SEGB) Josephson junctions with a YBa/sub 2/Cu/sub 3/O/sub 7-/spl delta// groundplane. The ADC consists of a quantizer connected to a Toggle flip-flop through a buffer-like stage. Direct readout of the flux state of the T flip-flop was made with a Read SQUID inductively coupled through a hole in the groundplane. The circuits were operated at 65 K and low speeds. The SNS circuits outperformed the SEGB circuits because of their higher readout voltages and tighter critical current spreads.
A new method of analyzing bit error rates (BERs) for SFQ circuits and their outputs at GHz speeds will be presented. This method was used to test four- and six-bit pseudorandom code generators. The code generators were operated in free-run mode, i.e., without a synchronization (Reset) pulse. This enabled us to conduct BER testing to much lower levels than when the code generator is operated in Reset mode. The SFQ circuit output was amplified with a superconducting output latch to give voltage levels suitable for display on a sampling scope. The GHz output data was analyzed by external computer software; this permitted extended tests without user supervision. With the code generators operating in free-run mode, they routinely gave bit error rates (BERs) in the 10/sup -11/ range; the best BER recorded was 1.1*10/sup -13/ (2 errors in /spl sim/2.5 hours) at 2 GHz. We have successfully tested these code generators at frequencies in excess of 3.5 GHz with BERs in the 10/sup -10/ range as well.
Single-flux quantum devices are used in superconductive analog-to-digital converters (ADCs), shift registers, and memory cells. They have been proposed for logic applications. The authors report the performance of high-speed superconducting, single-flux quantum (SFQ) ripple counters. Both memory and logic functions of the counter are investigated. Errors in logic operation produce bit error rates (BERs) as low as 0.22 errors per million binary operations, measured while counting 100-MHz pseudorandom input pulses. Errors in memory function do not occur on the time scale of the measurements. The BER is shown to be nearly independent of input bit rate and pattern, but strongly dependent on the counter cell operating point.< >
We describe the design of an oversampling single-flux-counting analog-to-digital converter with the estimated bandwidth of a few tens of MHz, based on Rapid Single-Flux-Quantum (RSFQ) devices. It consists of an input analog circuit, high-speed quantizer with an original analog/digital negative feedback loop, decimation (comb) filter, and supporting subsystems including clock distribution circuits, quantization signal conditioner, and output drivers. We have applied a new approach, the 'symmetrizing' negative feedback, to free the quantizer from the intrinsic hysteresis without dynamic range sacrifice. The 16-bit version of the system comprises about 1,500 Josephson junctions and consumes 1.2 mW of DC power, when implemented using Nb-trilayer technology with 1 kA/cm/sup 2/, 3.5 /spl mu/m Josephson junctions. All subsystems of the converter have been successfully tested and testing of the system as a whole is in progress.>