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IEEE Transactions on Electron Devices

Analog-to-digital conversion with unlatched SQUID's

John P. Hurrell, David C. Pridmore-Brown, Arnold H. Silver

Published Oct 1, 1980• 77 citations
Publisher

Abstract

Digital Josephson circuits that do not latch into the voltage state provide an opportunity for high-speed serial processing. These fast logic gates must ultimately generate and record small fast pulses generated by single fluxoid events. This is demonstrated in a concept for a high-speed analog-to-digital (A/D) converter. Low β-value unlatched SQUID's are used throughout for ultimate speed, sensitivity, and simplicity. The analog signal is quantized by a single-junction SQUID and converted into a pulse train resulting from fluxoid transitions. These are counted in a chain of bistable two-junction SQUID's which successively scale the pulse train by a factor 2. These SQUID's perform both logic and memory functions at the single fluxoid level. The bit count stored in the array is gated out each sampling interval to provide the digitized signal. The performance of this device has been simulated and criteria established for the unlatched SQUID design. These include dimensionality, impedance, damping, intra- and inter-SQUID delays and β factor. Large analog dynamic range is available with the high intrinsic linearity of the SQUID quantizer and a long chain of scalers.

DOI
10.1109/t-ed.1980.20126

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Digital Josephson circuits that do not latch into the voltage state provide an opportunity for high-speed serial processing. These fast logic gates must ultimately generate and record small fast pulses generated by single fluxoid events. This is demonstrated in a concept for a high-speed analog-to-digital (A/D) converter. Low β-value unlatched SQUID's are used throughout for ultimate speed, sensitivity, and simplicity. The analog signal is quantized by a single-junction SQUID and converted into a pulse train resulting from fluxoid transitions. These are counted in a chain of bistable two-junction SQUID's which successively scale the pulse train by a factor 2. These SQUID's perform both logic and memory functions at the single fluxoid level. The bit count stored in the array is gated out each sampling interval to provide the digitized signal. The performance of this device has been simulated and criteria established for the unlatched SQUID design. These include dimensionality, impedance, damping, intra- and inter-SQUID delays and β factor. Large analog dynamic range is available with the high intrinsic linearity of the SQUID quantizer and a long chain of scalers.
High speed, single flux quantum (SFQ) binary scalers are important components in superconducting analog-to-digital converters (ADC). This paper reviews the concept for a SQUID ADC and the design of an SFQ binary ripple counter, and reports the simulation of key components, and fabrication and performance of non-latching SQUID scalers and SFQ binary ripple counters. The SQUIDs were fabricated with Nb/Nb2O5/PbIn junctions and interconnected by monolithic-superconducting transmission lines and isolation resistors. Each SQUID functioned as a bistable flip-flop with the input connected to the center of the device and the output across one junction. All junctions were critically damped to optimize the pulse response. Operation was verified by observing the do I-V curves of successive SQUIDs driven by a cw pulse train generated on the same chip. Each SQUID exhibited constant-voltage current steps at 1/2 the voltage of the preceding device as expected from the Josephson voltage-to-frequency relation. Steps were observed only for the same voltage polarity of successive devices and for proper phase bias of the SQUID. Binary frequency division was recorded up to 40GHz for devices designed to operate to 28GHz.
A superconducting loop containing a Josephson junction develops voltage pulses when it admits and expels magnetic flux quanta, and thus may be used as an A/D converter. We here develop and discuss several conditions which must be satisfied for the generation by the SQUID of an unambiguously countable pulse train, from which the analog signal can be faithfully reconstructed. These conditions can be satisfied over a broad range of realizable values of inductance and resistance. The capacitance, however, must be carefully controlled. The results of simulations are also presented, illustrating the various ways in which the pulse trains are affected.
Successful utilization of the quasi one-junction SQUID (QOS) as a signal comparator for analog-to-digital conversion (ADC) has been demonstrated by several groups, This idea is extended to show how similar comparators can be integrated into an all rapid single flux quantum (RSFQ) digital architecture. Comparators are interrogated by SFQ sampling pulses and in turn give output according to the RSFQ convention. One- and two-bit ADC's have been simulated, fabricated and tested at low speed. Total performance of these devices is estimated within the framework of a multiple bit parallel flash ADC architecture.>
We describe the design of an oversampling single-flux-counting analog-to-digital converter with the estimated bandwidth of a few tens of MHz, based on Rapid Single-Flux-Quantum (RSFQ) devices. It consists of an input analog circuit, high-speed quantizer with an original analog/digital negative feedback loop, decimation (comb) filter, and supporting subsystems including clock distribution circuits, quantization signal conditioner, and output drivers. We have applied a new approach, the 'symmetrizing' negative feedback, to free the quantizer from the intrinsic hysteresis without dynamic range sacrifice. The 16-bit version of the system comprises about 1,500 Josephson junctions and consumes 1.2 mW of DC power, when implemented using Nb-trilayer technology with 1 kA/cm/sup 2/, 3.5 /spl mu/m Josephson junctions. All subsystems of the converter have been successfully tested and testing of the system as a whole is in progress.>
This paper presents the progress we have made on our design, fabrication, and testing of a fully parallel superconducting analog-to-digital converter (ADC) with multi-GHz clock frequencies and input bandwidth. To our best knowledge, this converter is the first flash-type analog-to-digital converter ever reported in Josephson technology that fully integrates a quantizer and a thermometer-to-binary encoder to achieve binary outputs. In this design, the quantizer consists of 2(superscript N-1 comparators, each of which is realized using a hysteretic one- junction sampling SQUID driving a two-junction readout SQUID. A new logic family has been designed based on the same comparator building block and has been used to implement the thermometer-to- binary encoder. Taking advantage of the fact that the encoder's input is thermometer-coded, we have designed three-input and four-input quasi-XOR gates with only three NAND gates and therefore reduced significantly the total gate count. Functionalities of all the sub-circuits have been verified experimentally at clock frequencies up to 3 GHz, which is limited by our currently available testing equipment.
A new family of counter-type Josephson-junction A/D converters using ultrafast rapid single-flux quantum (RSFQ) logic/memory elements is proposed. The converters are built in two main blocks: a low-bit differential-code A/D converter running with subterahertz clock speed and a RSFQ-logic-based digital processing unit providing digital low-pass filtering and sample rate reduction. It is shown that such converters can be treated as digital SQUIDs possessing an extremely high slew rate (up to 10/sup 11/ phi /sub 0//s) combined with flux resolution close to that of analog DC SQUIDs (up to 10/sup -6/ phi /sub 0/Hz/sup -1/2/). Several ways of implementing both main blocks to make it possible to tradeoff these parameters against converter complexity are presented and discussed.