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Journal of Physics Conference Series

High-speed single flux-quantum up/down counter for neural computation using stochastic logic

Takeshi Onomi, Takaharu Kondo, Kiyotaka Nakajima

Published Feb 1, 2008• 7 citations
Publisher

Abstract

We propose the high-speed single flux-quantum(SFQ) up/down counter for the neural computation using stochastic logic. Up and down signals are counted by two independent counters, respectively. The proposed counter circuit can count SFQ signals of 50GHz with large operation margins. To realize the up/down counter, we fabricated a 2-bit up counter circuit and a 2-bit down counter circuit as basic blocks by Nb integrated circuits. The low-speed test results of these circuits show correct operations. We also measured dc voltages of Josephson transmission lines to investigate the responses of carry operations for SFQ pulse trains. The results show that the counter circuits have potential to count 144GHz SFQ pulses.

DOI
10.1088/1742-6596/97/1/012187

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We propose the high-speed single flux-quantum(SFQ) up/down counter for the neural computation using stochastic logic. Up and down signals are counted by two independent counters, respectively. The proposed counter circuit can count SFQ signals of 50GHz with large operation margins. To realize the up/down counter, we fabricated a 2-bit up counter circuit and a 2-bit down counter circuit as basic blocks by Nb integrated circuits. The low-speed test results of these circuits show correct operations. We also measured dc voltages of Josephson transmission lines to investigate the responses of carry operations for SFQ pulse trains. The results show that the counter circuits have potential to count 144GHz SFQ pulses.
We report a design and an experimental result of an SFQ up/down counter for neural computation using stochastic logic. Neural computation using stochastic logic must accumulate the pulses in order to generate the membrane potential of a neuron. A high-speed up/down counter is necessary to achieve high-speed operation. The proposed up/down counter has two operation phases which are the accumulation of signals and the access of accumulation result. Even if the number of bit increases, the operation speed of the accumulation does not decrease in this method. A 4-bit up/down counter is fabricated using niobium-trilayer standard process and successfully demonstrated. The numerical simulation shows that the up/down counter can operate up to 70 GHz with an enough bias margin in the accumulation phase.
Abstract Superconducting single flux quantum (SFQ) circuits can operate at ultrafast speeds, and their superconducting random number generators (SRNGs) produce high-quality stochastic bit sequences at several tens GHz, with an arbitrary probability of outputting ‘1’, making them ideal for stochastic computing. The conventional superconducting stochastic adder uses a multiplexer (MUX) controlled by a random bit sequence generated by the SRNG. However, the SFQ-based MUX occupies a large circuit area, and any deviation in the probability of the control signal directly degrades the accuracy of stochastic addition. To overcome these limitations, we propose a deterministic stochastic adder comprising only an AND gate, an XOR gate, and a toggle flip-flop. Our design outputs one ‘1’ for every two input ‘1’s, achieving stochastic addition without the random control signal. Compared to the MUX-based stochastic adder, the proposed adder reduces the root-mean-square error by a factor of 32 when adding 1024-bit random sequences, reduces circuit area by 49.0%, and Josephson junction count by 28.1%, while supporting operating frequencies of about 120 GHz in simulation. We fabricated the proposed adder with two SRNGs for generating input sequences using a 10 kA cm −2 Nb four-layer superconducting process. High-speed operation was verified up to approximately 35.4 GHz with a constant bias margin by measuring the average voltage at the input and outputs. To the best of our knowledge, this is the first demonstration of ultrafast stochastic arithmetic operations above 30 GHz.
Abstract A superconducting single-flux-quantum (SFQ) circuit is suitable for stochastic computation that represents information in terms of the probability of ‘1’s in a finite-bit-length number train, due to its high-speed operation. In this paper, we demonstrate a matrix multiplier based on the SFQ logic circuits and superconductive random number generators (SRNGs). The stochastic multiplier required for the matrix product calculation is implemented using an AND gate. The stochastic adder is implemented by a multiplexer where the random number train generated by the SRNG is utilized as a control signal. We implemented 2 × 2 matrix multiplier targeting a frequency of 50 GHz, using the 10 kA cm −2 Nb 4-layer superconductor circuit fabrication process. Numerical calculation results show that the designed stochastic matrix multiplier can multiply with a computational error of 1.12% when the input stochastic numbers are 1000-bit number trains. In the measurements, the input stochastic numbers were also generated by SRNGs, and the operation of the test circuit was verified. We experimentally demonstrated the correct operation of the matrix multiplier, and the obtained calculation errors agreed with theoretical values. To the best of our knowledge, this is the first demonstration of stochastic arithmetic operation using SFQ circuits.
Single-flux-quantum (SFQ) technology is a novel technology where binary information is represented by a single flux. It enables us to realize high-speed, low-power SFQ logic circuits, surpassing conventional complementary metal-oxide-silicon (CMOS) technology. We proposed an SFQ packet switch to avoid the bottlenecks in broadband networks of the future. To demonstrate high-speed operation of an SFQ logic circuit and its application to our switch architecture, we designed a cross/bar switch. It consists of 13 logic gates and 581 Josephson junctions were used in the layout. We confirmed correct operations up to 33 GHz in simulation. We placed the switch circuit in an on-chip test system for high-speed (over 10 GHz) test. Including I/O circuits, the system as a whole consists of 1236 Josephson junctions. The chip was fabricated by using NEC's standard Nb process. We carried out an on-chip test and found correct operations up to 35 GHz.
We have been developing a single-flux-quantum (SFQ) cross-bar switch, which is a main component of a network packet switch. We think that a network switch is an application in which the high speed of SFQ technology would be advantageous. Anticipating general and large-scale SFQ logic circuit design, we used the cell-based design method and the CONNECT standard SFQ cell library. The two-input and two-output cross-bar switch, a core switch component, consists of 13 logic cells connected by Josephson-transmission-line (JTL) cells. Because of the large size of JTL cells and the large delay in them, timing adjustment becomes more difficult as the operating speed and circuit size increase. After using a commercially available automatic router to find appropriate routes efficiently, we used a static timing analyzer for fine timing adjustment. Timing violations were fixed by changing JTL path delays using the tools we developed. The target operating frequency of the switch was 40 GHz, which corresponds to a clock period of 25 ps. Careful timing adjustment was necessary to ensure correct operations at such a high speed. The test chip was fabricated by using an NEC standard Nb process. The circuit, including on-chip test circuitry, was composed of about 1500 Josephson junctions. We confirmed its correct operations up to 50 GHz with a bias margin of /spl plusmn/20%.
A single flux quantum (SFQ) logic cell library has been developed for the 10kA/cm2 Nb multi-layer fabrication process to efficiently design large-scale SFQ digital circuits. In the new cell library, the critical current density of Josephson junctions is increased from 2.5kA/cm2 to 10kA/cm2 compared to our conventional cell library, and the McCumber-Stwart parameter of each Josephson junction is increased to 2 in order to increase the circuit operation speed. More than 300 cells have been designed, including fundamental logic cells and wiring cells for passive interconnects. We have measured all cells and confirmed they stably operate with wide operating margins. On-chip high-speed test of the toggle flip-flop (TFF) cell has been performed by measuring the input and output voltages. The TFF cell at the input frequency of up to 400GHz was confirmed to operate correctly. Also, several fundamental digital circuits, a 4-bit concurrent-flow shift register and a bit-serial adder have been designed using the new cell library, and the correct operations of the circuits have been demonstrated at high clock frequencies of more than 100GHz.