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IEEE Transactions on Applied Superconductivity

Implementation of High-Speed Single Flux-Quantum Up/Down Counter for the Neural ComputationUsing Stochastic Logic

Takeshi Onomi, Takaharu Kondo, Kiyotaka Nakajima

Published Jun 1, 2009• 14 citations
Publisher

Abstract

We report a design and an experimental result of an SFQ up/down counter for neural computation using stochastic logic. Neural computation using stochastic logic must accumulate the pulses in order to generate the membrane potential of a neuron. A high-speed up/down counter is necessary to achieve high-speed operation. The proposed up/down counter has two operation phases which are the accumulation of signals and the access of accumulation result. Even if the number of bit increases, the operation speed of the accumulation does not decrease in this method. A 4-bit up/down counter is fabricated using niobium-trilayer standard process and successfully demonstrated. The numerical simulation shows that the up/down counter can operate up to 70 GHz with an enough bias margin in the accumulation phase.

DOI
10.1109/tasc.2009.2018477

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We report a design and an experimental result of an SFQ up/down counter for neural computation using stochastic logic. Neural computation using stochastic logic must accumulate the pulses in order to generate the membrane potential of a neuron. A high-speed up/down counter is necessary to achieve high-speed operation. The proposed up/down counter has two operation phases which are the accumulation of signals and the access of accumulation result. Even if the number of bit increases, the operation speed of the accumulation does not decrease in this method. A 4-bit up/down counter is fabricated using niobium-trilayer standard process and successfully demonstrated. The numerical simulation shows that the up/down counter can operate up to 70 GHz with an enough bias margin in the accumulation phase.
We propose the high-speed single flux-quantum(SFQ) up/down counter for the neural computation using stochastic logic. Up and down signals are counted by two independent counters, respectively. The proposed counter circuit can count SFQ signals of 50GHz with large operation margins. To realize the up/down counter, we fabricated a 2-bit up counter circuit and a 2-bit down counter circuit as basic blocks by Nb integrated circuits. The low-speed test results of these circuits show correct operations. We also measured dc voltages of Josephson transmission lines to investigate the responses of carry operations for SFQ pulse trains. The results show that the counter circuits have potential to count 144GHz SFQ pulses.
Abstract A superconducting single-flux-quantum (SFQ) circuit is suitable for stochastic computation that represents information in terms of the probability of ‘1’s in a finite-bit-length number train, due to its high-speed operation. In this paper, we demonstrate a matrix multiplier based on the SFQ logic circuits and superconductive random number generators (SRNGs). The stochastic multiplier required for the matrix product calculation is implemented using an AND gate. The stochastic adder is implemented by a multiplexer where the random number train generated by the SRNG is utilized as a control signal. We implemented 2 × 2 matrix multiplier targeting a frequency of 50 GHz, using the 10 kA cm −2 Nb 4-layer superconductor circuit fabrication process. Numerical calculation results show that the designed stochastic matrix multiplier can multiply with a computational error of 1.12% when the input stochastic numbers are 1000-bit number trains. In the measurements, the input stochastic numbers were also generated by SRNGs, and the operation of the test circuit was verified. We experimentally demonstrated the correct operation of the matrix multiplier, and the obtained calculation errors agreed with theoretical values. To the best of our knowledge, this is the first demonstration of stochastic arithmetic operation using SFQ circuits.
Abstract Superconducting single flux quantum (SFQ) circuits can operate at ultrafast speeds, and their superconducting random number generators (SRNGs) produce high-quality stochastic bit sequences at several tens GHz, with an arbitrary probability of outputting ‘1’, making them ideal for stochastic computing. The conventional superconducting stochastic adder uses a multiplexer (MUX) controlled by a random bit sequence generated by the SRNG. However, the SFQ-based MUX occupies a large circuit area, and any deviation in the probability of the control signal directly degrades the accuracy of stochastic addition. To overcome these limitations, we propose a deterministic stochastic adder comprising only an AND gate, an XOR gate, and a toggle flip-flop. Our design outputs one ‘1’ for every two input ‘1’s, achieving stochastic addition without the random control signal. Compared to the MUX-based stochastic adder, the proposed adder reduces the root-mean-square error by a factor of 32 when adding 1024-bit random sequences, reduces circuit area by 49.0%, and Josephson junction count by 28.1%, while supporting operating frequencies of about 120 GHz in simulation. We fabricated the proposed adder with two SRNGs for generating input sequences using a 10 kA cm −2 Nb four-layer superconducting process. High-speed operation was verified up to approximately 35.4 GHz with a constant bias margin by measuring the average voltage at the input and outputs. To the best of our knowledge, this is the first demonstration of ultrafast stochastic arithmetic operations above 30 GHz.
100-GHz Single-Flux-Quantum Bit-Serial Adder Based on 10-kA/cm2{\rm kA/cm}^{2}kA/cm2 Niobium Process
This paper reports the design and test results of a single-flux-quantum (SFQ) bit-serial adder, which we designed with a target-clock frequency of 100 GHz, to investigate several techniques for producing ultra-high-speed computations using SFQ circuits. The bit-serial adder was designed based on a new cell library developed for the ISTEC Advanced Process, where the critical current density and McCumber-Stewart parameters of Josephson junctions were increased to 10 kA/cm2and 2.0, respectively, to obtain higher operating frequencies. In addition, we adopted a circuit-design technique based on state transitions excluding a feedback loop in a typical bit-serial adder, and redesigned the NOR gate with the McCumber-Stewart parameter increased to 4.0 to improve performance. As a result, we experimentally obtained a sufficient dc bias margin of ±18% from low frequencies to 60 GHz, and verified the correctness of operations up to 93 GHz. We also demonstrated that the introduction of a higher bias voltage or large inductors in series with bias resistors is effective for achieving faster operation.
Abstract Stochastic computing (SC) is a form of probabilistic computation that encodes information in the probability of a ‘1’ occurring within a finite-length binary sequence. SC has been investigated for applications in various fields that do not require deterministic and precise computation. A superconducting single-flux-quantum (SFQ) circuit is considered a promising candidate for implementing SC hardware due to its high-speed operation and probabilistic behavior. In this study, we propose a novel large fan-out signal splitter to enable large-scale SFQ-based stochastic arithmetic circuits, addressing the issue of computation accuracy degradation caused by correlations between binary sequences. The proposed signal splitter generates uncorrelated output binary sequences by utilizing superconductor random number generators frequency-synchronized to the input binary sequence. The fan-out can be easily increased by simply adding more superconductor random number generators. We implemented a four-output stochastic number signal splitter using the 10 kA cm−2 Nb four-layer superconducting circuit fabrication process. Its operation was successfully demonstrated by measuring the average voltage at the input and outputs under continuous high-speed binary sequence input. High-speed operation up to 33.2 GHz was confirmed. The proposed signal splitter uniquely leverages the properties of superconducting circuits, where flux quanta determined by fundamental physical constants serve as the information carrier. We believe this development will significantly advance the realization of practical SFQ-based SC systems.
We propose an algorithm of digit-serial adders using single-flux-quantum (SFQ) circuits. The proposed digit-serial adder adapts the carry look-ahead (CLA) adder architecture to generate carry signals, which are generated from the digit-serial data and fed back internally to the following digit-serial data to increase the throughput of the calculation. We have designed and implemented a 4-bit digit-serial adder using the SRL 2.5kA/cm2 niobium standard process to demonstrate its high-speed operation. The total number of Josephson junctions is 2316. We have successfully tested full operations of the 4-bit digit-serial adder with a bias margin of ± 15% at 25GHz. Its maximum operation frequency was 30GHz.