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Superconductor Science and Technology

Large fan-out single-flux-quantum stochastic number splitter utilizing frequency-synchronized superconductor random number generators

Kaito Asaka, Nobuyuki Yoshikawa, Yuki Yamanashi

Published Mar 10, 2025• 4 citations
Publisher

Abstract

Abstract Stochastic computing (SC) is a form of probabilistic computation that encodes information in the probability of a ‘1’ occurring within a finite-length binary sequence. SC has been investigated for applications in various fields that do not require deterministic and precise computation. A superconducting single-flux-quantum (SFQ) circuit is considered a promising candidate for implementing SC hardware due to its high-speed operation and probabilistic behavior. In this study, we propose a novel large fan-out signal splitter to enable large-scale SFQ-based stochastic arithmetic circuits, addressing the issue of computation accuracy degradation caused by correlations between binary sequences. The proposed signal splitter generates uncorrelated output binary sequences by utilizing superconductor random number generators frequency-synchronized to the input binary sequence. The fan-out can be easily increased by simply adding more superconductor random number generators. We implemented a four-output stochastic number signal splitter using the 10 kA cm−2 Nb four-layer superconducting circuit fabrication process. Its operation was successfully demonstrated by measuring the average voltage at the input and outputs under continuous high-speed binary sequence input. High-speed operation up to 33.2 GHz was confirmed. The proposed signal splitter uniquely leverages the properties of superconducting circuits, where flux quanta determined by fundamental physical constants serve as the information carrier. We believe this development will significantly advance the realization of practical SFQ-based SC systems.

DOI
10.1088/1361-6668/adbec3

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Abstract Stochastic computing (SC) is a form of probabilistic computation that encodes information in the probability of a ‘1’ occurring within a finite-length binary sequence. SC has been investigated for applications in various fields that do not require deterministic and precise computation. A superconducting single-flux-quantum (SFQ) circuit is considered a promising candidate for implementing SC hardware due to its high-speed operation and probabilistic behavior. In this study, we propose a novel large fan-out signal splitter to enable large-scale SFQ-based stochastic arithmetic circuits, addressing the issue of computation accuracy degradation caused by correlations between binary sequences. The proposed signal splitter generates uncorrelated output binary sequences by utilizing superconductor random number generators frequency-synchronized to the input binary sequence. The fan-out can be easily increased by simply adding more superconductor random number generators. We implemented a four-output stochastic number signal splitter using the 10 kA cm−2 Nb four-layer superconducting circuit fabrication process. Its operation was successfully demonstrated by measuring the average voltage at the input and outputs under continuous high-speed binary sequence input. High-speed operation up to 33.2 GHz was confirmed. The proposed signal splitter uniquely leverages the properties of superconducting circuits, where flux quanta determined by fundamental physical constants serve as the information carrier. We believe this development will significantly advance the realization of practical SFQ-based SC systems.
Abstract Superconducting single flux quantum (SFQ) circuits can operate at ultrafast speeds, and their superconducting random number generators (SRNGs) produce high-quality stochastic bit sequences at several tens GHz, with an arbitrary probability of outputting ‘1’, making them ideal for stochastic computing. The conventional superconducting stochastic adder uses a multiplexer (MUX) controlled by a random bit sequence generated by the SRNG. However, the SFQ-based MUX occupies a large circuit area, and any deviation in the probability of the control signal directly degrades the accuracy of stochastic addition. To overcome these limitations, we propose a deterministic stochastic adder comprising only an AND gate, an XOR gate, and a toggle flip-flop. Our design outputs one ‘1’ for every two input ‘1’s, achieving stochastic addition without the random control signal. Compared to the MUX-based stochastic adder, the proposed adder reduces the root-mean-square error by a factor of 32 when adding 1024-bit random sequences, reduces circuit area by 49.0%, and Josephson junction count by 28.1%, while supporting operating frequencies of about 120 GHz in simulation. We fabricated the proposed adder with two SRNGs for generating input sequences using a 10 kA cm −2 Nb four-layer superconducting process. High-speed operation was verified up to approximately 35.4 GHz with a constant bias margin by measuring the average voltage at the input and outputs. To the best of our knowledge, this is the first demonstration of ultrafast stochastic arithmetic operations above 30 GHz.
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A novel high-speed physical random number generator using the superconductive single-flux-quantum (SFQ) circuits and thermal noises in the circuit has been proposed. The proposed physical random number generator is similar to an SFQ balanced comparator. Thermal noises in shunt resisters are used to obtain random outputs. Because of the high-sensitivity of SFQ circuits, the true random numbers can be generated without amplification of the noises at high clock frequency. Generation of the true random numbers at the frequency of several tens GHz can be realized by using the proposed circuit. Moreover, the circuit scale of the proposed circuit is very small and the generation frequency of the random number generator can be easily enhanced by parallelizing the circuits. We have designed and tested the superconductive physical random number generator using the 2.5 kA/cm2Nb standard process and evaluated the quality of the generated random number train. We have examined a 220-bit random number train generated at a low frequency and no periodicity is observed. We believe that the superconductive physical random number generator can be applied to cryptographic applications for more secure information processing.
Maximum-length sequences (M-sequences) are known as pseudo-random numbers generated with relatively simple digital circuits. In this paper, we present a single-flux-quantum digital circuit that generated three output bits of a 4-bit M-sequence in one clock operation. The circuit comprised three clocked exclusive-or gates, one delay flip-flop, three dc/SFQ converters (for set, reset, and low-frequency clock signals), and three SFQ/dc converters (for three parallel outputs), all of which were integrated on a superconducting Nb chip. A 10-GHz clock generator was also implemented for high-speed testing. The total number of Nb/AlOx/Nb Josephson junctions was 568. Verilog simulation demonstrated correct circuit operation with a 20-GHz clock, which corresponded to the generation rate of 60 Gb/s. The measurement was carried out in a liquid helium bath. Low-speed testing with a 1-kHz clock demonstrated periodic signals of three parallelized 4-bit M-sequence. We also confirmed that the outputs were correctly shifted when 13 clock signals of 10 GHz were fed between two 1-kHz clock signals.
A hardware random number generator using Josephson oscillation and a few single flux quantum (SFQ) logic gates is presented. The logic circuit of the random number generator consists of one toggle flip flop and one and gate. A prototype random number generator is designed by logic cells based on a 2.5-kA/cm2Nb/AlOx/Nb integration process. The fundamental operation at a few hundred megahertz of the random number sampling frequency is confirmed by numerical simulation when a DC/SFQ converter is used for generating trigger signals. An additional delay line using an overdamped Josephson transmission line is used for increasing the timing jitter to get random numbers. The delay line makes it possible for the random number generator to operate over 1 GHz. To confirm the fundamental operation of the circuit, a primitive SFQ random number generator is fabricated using the AIST standard process with 2.5-kA/cm2Nb/AlOx/Nb junctions and the standard logic cell library. A random number generation based on a low-speed functional test is successfully confirmed.
Abstract Stochastic computing (SC) is a method of expressing a numerical value by the appearance ratio of 1 in a bitstream to perform an operation. Rapid single flux quantum (RSFQ) circuits can handle SC naturally and operate at ultra-high speed. RSFQ SC circuits are suitable for applications tolerating error. This paper presents a design method of RSFQ SC circuits to calculate polynomials. Using the proposed design method, an internal circuit is designed to feed bitstreams of coefficients from bitstreams of constant to reduce large stochastic number generators. The method inserts storage elements to reduce correlations of signals, and thereby reduce the calculation error of the circuit. Additionally, it minimizes the number of inserted D flip-flops utilizing the latching function of gate inputs of RSFQ logic gates.