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Superconductor Science and Technology

Bit error rate measurements on RSFQ circuits using a SQUID current comparator

Masaaki Maezawa, Fuminori Hirayama, Motohiro Suzuki

Published Mar 16, 2006• 0 citations
Publisher

Abstract

We propose a simple method of measuring bit error rates (BERs) for rapid single flux quantum (RSFQ) circuits operating at high frequencies. An error detector based on a SQUID current comparator, which operates without a timing clock, is employed to simplify the test system and measurements. We successfully investigated high-frequency operation of RSFQ cells that were utilized to implement our RSFQ digital-to-analogue converter for metrology applications. Sufficiently low BERs were demonstrated in the circuit operation at several tens of gigahertz.

DOI
10.1088/0953-2048/19/5/s35

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We propose a simple method of measuring bit error rates (BERs) for rapid single flux quantum (RSFQ) circuits operating at high frequencies. An error detector based on a SQUID current comparator, which operates without a timing clock, is employed to simplify the test system and measurements. We successfully investigated high-frequency operation of RSFQ cells that were utilized to implement our RSFQ digital-to-analogue converter for metrology applications. Sufficiently low BERs were demonstrated in the circuit operation at several tens of gigahertz.
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We report experimental results of bit-error-rate (BER) measurements in small-critical-current or lowered-biasvoltage rapid single-flux-quantum (RSFQ) circuits for power reduction. In such reduced-power RSFQ circuits, the BERs can be increased because of the reduced signal-to-noise ratio. We fabricated 2-bit shift registers using a 2.5-kA/cm2niobium process, and measured BERs by low-frequency tests at 4.2 K. We obtained sufficiently wide bias margins when we reduced the critical currents in a range of 1/2 to 1/4 of the conventional design, while it narrowed as the critical currents reduced to 1/8. For low-voltage shift registers, the bias margins linearly decreased in width as bias voltages were lowered. We found that 0.25 mV, 1/10 of the conventional design, was a good bias voltage to balance competing power reduction and bias margin.
The problem of fluctuation-induced digital errors in a rapid single flux quantum (RSFQ) circuit has been very important issue. So in this experiment, we calculated error rate of RSFQ switch in superconductiyity ALU, The RSFQ switch should have a very low error rate in the optimal bias. We prepared two circuits Placed in parallel. One was a 10 Josephson transmission lines (JTLs) connected in series, and the other was the same circuit but with an RSFQ switch placed in the middle of the 10 JTLs. We used a splitter to feed the same input signal to the both circuits. The outputs of the two circuits were compared with an RSFQ XOR to measure the error rate of the RSFQ switch. By using a computerized bit error rate test setup, we measured the bit error rate of 2.18 when the bias to the RSFQ switch was 0.398mh that was quite off from the optimum bias of 0.6mA.
The application of high temperature superconductor (HTS) Josephson junctions in digital rapid single flux quantum circuits requires a careful study of the influence of thermal noise on the bit error rate (BER). We have determined experimentally, for the first time, the BER of a HTS rapid single flux quantum circuit. A comparator, formed by two Josephson junctions, was integrated in a Josephson transmission line ring oscillator, allowing us to perform high speed testing of the comparator at GHz frequencies. For fabrication, focused-electron-beam-irradiated junctions have been used because of their small parameter spread and excellent alignment possibilities. A BER of less than 10−11 was obtained at 39 K.
A low-skew frequency divider and clock controller have been designed for high-frequency timing of superconductor rapid single-flux-quantum (RSFQ) digital systems. The circuits have only about 10-ps skew between input and output signals and are applicable for multirate digital systems (e,g., oversampling analog-to-digital converter and bit-serial digital systems). Several circuits have been fabricated in conventional Nb-trilayer technology with a critical current density of 1 kA/cm/sup 2/. The most complex clock controller generates trains of 2/sup 24/ single-flux-quantum pulses with a period of less than 70 ps. The long-term relative stability of these intervals has been measured to be better than 6/spl times/10/sup -5/. The basic component of the controller, a frequency divider, operates at input frequencies above 85 GHz.>