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IEEE Transactions on Magnetics

Josephson counting analog-to-digital converter

Donald L. Miller, John X. Przybysz, J.H. Kang, C.A. Hamilton, D.M. Burnell

Published Mar 1, 1991• 21 citations
Publisher

Abstract

A superconductive analog-to-digital converter which uses a DC SQUID as a quantizer and a flip-flop counter as a digitizer has been designed, fabricated, and tested. The circuit was fabricated using a ten-level niobium process. Tests at 4.2 K demonstrated counting to the full 12-b accuracy of the design, monotonic A/D conversion with linearity to less than 1 LSB over the more than 9-b range of conversion, read-on-the-fly operation with counter overflow, and counter operation with a gate current bus.

DOI
10.1109/20.133783

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IEEE Transactions on Applied Superconductivity•Jun 1, 1997•25 citations
A superconductive analog-to-digital converter which uses a DC SQUID as a quantizer and a flip-flop counter as a digitizer has been designed, fabricated, and tested. The circuit was fabricated using a ten-level niobium process. Tests at 4.2 K demonstrated counting to the full 12-b accuracy of the design, monotonic A/D conversion with linearity to less than 1 LSB over the more than 9-b range of conversion, read-on-the-fly operation with counter overflow, and counter operation with a gate current bus.
We have characterized Nb analog to digital converters using a resistor-coupled SFQ flip flop counter and a latching destructive readout (DRO). The counter used SFQ buffers between bits to provide isolation during destructive readout. We have measured parallel readout at sample rates up to 125 MSPS. We have also successfully operated an ADC which has Josephson junction regulated flip flop gate and readout bias busses. Using a self-resetting gate (SRG) at the carry out of the counter, we have measured the bit error rates (BER) of the counters. A two junction SQUID quantizer, biased in the voltage state, was used to produce correlated SFQ pulses at each junction. The SRG outputs of two 10 bit counters connected to the two quantizer outputs were compared. We measured a BER of /spl sim/5/spl times/10/sup -11/ with the quantizer operating at 19 GHz. We believe the principle error source is the latching SRG.
We have fabricated and measured high T/sub c/ superconductor single flux quantum 1-bit flux-counting analog-to-digital converters (ADCs). The ADCs were made with a multilayer all-epitaxial process which incorporates 10 edge SNS (superconductor-normal-superconductor) or step-edge grain boundary (SEGB) Josephson junctions with a YBa/sub 2/Cu/sub 3/O/sub 7-/spl delta// groundplane. The ADC consists of a quantizer connected to a Toggle flip-flop through a buffer-like stage. Direct readout of the flux state of the T flip-flop was made with a Read SQUID inductively coupled through a hole in the groundplane. The circuits were operated at 65 K and low speeds. The SNS circuits outperformed the SEGB circuits because of their higher readout voltages and tighter critical current spreads.
This paper presents the progress we have made on our design, fabrication, and testing of a fully parallel superconducting analog-to-digital converter (ADC) with multi-GHz clock frequencies and input bandwidth. To our best knowledge, this converter is the first flash-type analog-to-digital converter ever reported in Josephson technology that fully integrates a quantizer and a thermometer-to-binary encoder to achieve binary outputs. In this design, the quantizer consists of 2(superscript N-1 comparators, each of which is realized using a hysteretic one- junction sampling SQUID driving a two-junction readout SQUID. A new logic family has been designed based on the same comparator building block and has been used to implement the thermometer-to- binary encoder. Taking advantage of the fact that the encoder's input is thermometer-coded, we have designed three-input and four-input quasi-XOR gates with only three NAND gates and therefore reduced significantly the total gate count. Functionalities of all the sub-circuits have been verified experimentally at clock frequencies up to 3 GHz, which is limited by our currently available testing equipment.
Digital Josephson circuits that do not latch into the voltage state provide an opportunity for high-speed serial processing. These fast logic gates must ultimately generate and record small fast pulses generated by single fluxoid events. This is demonstrated in a concept for a high-speed analog-to-digital (A/D) converter. Low β-value unlatched SQUID's are used throughout for ultimate speed, sensitivity, and simplicity. The analog signal is quantized by a single-junction SQUID and converted into a pulse train resulting from fluxoid transitions. These are counted in a chain of bistable two-junction SQUID's which successively scale the pulse train by a factor 2. These SQUID's perform both logic and memory functions at the single fluxoid level. The bit count stored in the array is gated out each sampling interval to provide the digitized signal. The performance of this device has been simulated and criteria established for the unlatched SQUID design. These include dimensionality, impedance, damping, intra- and inter-SQUID delays and β factor. Large analog dynamic range is available with the high intrinsic linearity of the SQUID quantizer and a long chain of scalers.
We describe the design of an oversampling single-flux-counting analog-to-digital converter with the estimated bandwidth of a few tens of MHz, based on Rapid Single-Flux-Quantum (RSFQ) devices. It consists of an input analog circuit, high-speed quantizer with an original analog/digital negative feedback loop, decimation (comb) filter, and supporting subsystems including clock distribution circuits, quantization signal conditioner, and output drivers. We have applied a new approach, the 'symmetrizing' negative feedback, to free the quantizer from the intrinsic hysteresis without dynamic range sacrifice. The 16-bit version of the system comprises about 1,500 Josephson junctions and consumes 1.2 mW of DC power, when implemented using Nb-trilayer technology with 1 kA/cm/sup 2/, 3.5 /spl mu/m Josephson junctions. All subsystems of the converter have been successfully tested and testing of the system as a whole is in progress.>
We have designed, fabricated, and successfully tested a Time-to-Digital converter (TDC). The TDC circuit consists of superconductive counters based on toggle flip-flops with destructive readout, shift registers, parallel-to-serial converters, and pulse detectors. The value of the counter is latched while the counter is operating at full speed. The TDC resolution is directly determined by the maximum counter speed, or 50 ps for an available 20 GHz clock rate. The circuits are implemented in HYPRES' standard Nb process with a critical current density of 1.0 kA/cm/sup 2/ using HYPRES' library of standard RSFQ cells.