Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

IEEE Transactions on Applied Superconductivity

Time-to-digital converters based on RSFQ digital counters

Oleg A. Mukhanov, Sergey V. Rylov

Published Jun 1, 1997• 25 citations
Publisher

Abstract

We have designed, fabricated, and successfully tested a Time-to-Digital converter (TDC). The TDC circuit consists of superconductive counters based on toggle flip-flops with destructive readout, shift registers, parallel-to-serial converters, and pulse detectors. The value of the counter is latched while the counter is operating at full speed. The TDC resolution is directly determined by the maximum counter speed, or 50 ps for an available 20 GHz clock rate. The circuits are implemented in HYPRES' standard Nb process with a critical current density of 1.0 kA/cm/sup 2/ using HYPRES' library of standard RSFQ cells.

DOI
10.1109/77.621788

Related papers

Timing circuits for RSFQ digital systems

Jao-Ching Lin, Vasili K. Semenov

A low-skew frequency divider and clock controller have been designed for high-frequency timing of superconductor rapid single-flux-quantum (RSFQ) digital systems. The circuits have only about 10-ps skew between input and output signals and are applicable for multirate digital systems (e,g., oversampling analog-to-digital converter and bit-serial digital systems). Several circuits have been fabricated in conventional Nb-trilayer technology with a critical current density of 1 kA/cm/sup 2/. The most complex clock controller generates trains of 2/sup 24/ single-flux-quantum pulses with a period of less than 70 ps. The long-term relative stability of these intervals has been measured to be better than 6/spl times/10/sup -5/. The basic component of the controller, a frequency divider, operates at input frequencies above 85 GHz.>

IEEE Transactions on Applied Superconductivity•Jan 1, 1995•37 citations

Demonstration of Picosecond Time Resolution in Double-Oscillator Time-to-Digital Converter Using Single-Flux-Quantum Circuits

Yuma Tomitsuka, Yuki Yamanashi, Nobuyuki Zen +2 more

We have been developing a time-to-digital converter (TDC) using single-flux-quantum (SFQ) circuits in order to realize an imaging system based on a superconducting strip single-photon detector (SSPD). In this system, the absorption position of a single photon in a meander-shaped SSPD is determined by measuring the delay time of the detected signal propagating through an SSPD delay line. Increasing the time resolution of the TDC is the primary concern for improving the spatial resolution of the system. Here we focused on the double-oscillator SFQ TDC, where the difference of oscillation periods between two SFQ ring oscillators determines the time resolution. In the previous study, a time resolution of about 4 ps was demonstrated by using the Nb standard Josephson integrated circuit (IC) process with a critical current density of 2.5 kA/cm2. In this study, we improved the time resolution by adopting the Nb advanced Josephson IC process with a critical current density of 10 kA/cm2and by optimizing the circuit parameters of the coincidence detector. The histogram and the linearity of the delay measurements show that the time resolution is improved to up to 2 ps.

IEEE Transactions on Applied Superconductivity•Mar 1, 2019•6 citations

Counting SFQ analog to digital converter results

Robert D. Sandell, D.J. Durand, Bruce J. Dalrymple +1 more

We have characterized Nb analog to digital converters using a resistor-coupled SFQ flip flop counter and a latching destructive readout (DRO). The counter used SFQ buffers between bits to provide isolation during destructive readout. We have measured parallel readout at sample rates up to 125 MSPS. We have also successfully operated an ADC which has Josephson junction regulated flip flop gate and readout bias busses. Using a self-resetting gate (SRG) at the carry out of the counter, we have measured the bit error rates (BER) of the counters. A two junction SQUID quantizer, biased in the voltage state, was used to produce correlated SFQ pulses at each junction. The SRG outputs of two 10 bit counters connected to the two quantizer outputs were compared. We measured a BER of /spl sim/5/spl times/10/sup -11/ with the quantizer operating at 19 GHz. We believe the principle error source is the latching SRG.

IEEE Transactions on Applied Superconductivity•Jun 1, 1997•0 citations

Low-Power Digital Readout Circuit for Superconductor Nanowire Single-Photon Detectors

Anubhav Sahu, M. Celik, Dmitri E. Kirichenko +2 more

We designed and tested the digital readout circuitry for superconducting nanowire single-photon detectors (SNSPDs). The designed time-to-digital converter (TDC) comprises a decision-making block, a clock controller, and a counter with parallel-to-serial (P2S) interface. We also designed an on-chip pattern generator to imitate a digitized SNSPD response that allowed us to screen the circuitry without bonding actual SNSPDs. Both rapid single-flux quantum (RSFQ) and its energy-efficient rapid single-flux quantum (ERSFQ) versions were designed for comparison and debugging purposes. To optimize the design of the feeding Josephson transmission line (FJTL) required by the ERSFQ variant, we compared different power grid structures and types of FJTLs. Using an 8-bit counter with P2S interface as a device under test, we also investigated the effect of FJTL's size on the bias margins. FJTL with a 75% junction overhead is sufficient for the ERSFQ circuit to match the margins of its RSFQ counterpart. All chips have been fabricated at MIT-LL using the SFQ5ee process node. Experimental results and future research directions are presented.

IEEE Transactions on Applied Superconductivity•Mar 18, 2019•17 citations

Experimental Validation of Key Elemental Circuits for RSFQ All-Digital Phase Locked Loop

Yoshinao Mizugaki, Daiki Fukuyo

Abstract An all-digital phase-locked loop (ADPLL) is a critical component for generating a precise clock sequence synchronized to a reference signal. For applications in superconducting qubit control, RSFQ ADPLL technology is promising due to its high-speed operation, low power consumption, and cryogenic compatibility. In this paper, we present the experimental validation of key elemental circuits for an improved RSFQ ADPLL: a digitally controlled oscillator (DCO), a time-to-digital converter (TDC), a buffer circuit in the proportional-differential (PD) controller, and a DCO controller. These test circuits were fabricated using a 10 kA/cm 2 Nb/AlO x /Nb process and characterized in a liquid helium bath. The experimental results demonstrated the successful operation of each circuit. Specifically, the DCO exhibited linear frequency control, and the TDC correctly generated digital signals according to the input time slots. The functional integrity of the PD controller’s buffer and the DCO controller was also confirmed. These results provide a foundation for the full integration of the RSFQ ADPLL.

Journal of Physics Conference Series•Jul 1, 2026•0 citations

Asynchronous circuits and systems in superconducting RSFQ digital technology

Z.J. Deng, Nobuyuki Yoshikawa, J. Tierno +2 more

Superconductive Rapid Single Flux Quantum (RSFQ) logic and memory, in which ones and zeros are represented by the presence or absence within a timing window of quantized picosecond voltage pulse (/spl int/v(t)dt=h/2e=2.07 mV/spl middot/ps), corresponding to one SFQ, can be integrated into a digital computing system with an operating rate of several tens of GHz, based on the present Nb Josephson junction integrated circuit technology. It is the most promising technology beyond semiconductor transistors for low-power high-end computation. However, as the operating speed of circuits and systems increase, timing uncertainty from fabrication process variations makes global synchronization very hard. In this paper, we present a globally asynchronous, locally synchronous timing methodology for RSFQ digital design, which can solve the global synchronization problem. We also demonstrate the recent experimental results of some asynchronous circuits and systems implemented in RSFQ technology. Several key components such as a self-timed shift register, a self-timed demultiplexor, a Muller-C element, a completion detector, and a clock generator have been designed and tested. High speed operation has been confirmed up to 20 Gb/s for a prototype data buffer system, which consists two self-timed shift registers and an on-chip 5-38 GHz clock generator.

IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)•Nov 27, 2002•7 citations
We have designed, fabricated, and successfully tested a Time-to-Digital converter (TDC). The TDC circuit consists of superconductive counters based on toggle flip-flops with destructive readout, shift registers, parallel-to-serial converters, and pulse detectors. The value of the counter is latched while the counter is operating at full speed. The TDC resolution is directly determined by the maximum counter speed, or 50 ps for an available 20 GHz clock rate. The circuits are implemented in HYPRES' standard Nb process with a critical current density of 1.0 kA/cm/sup 2/ using HYPRES' library of standard RSFQ cells.
A low-skew frequency divider and clock controller have been designed for high-frequency timing of superconductor rapid single-flux-quantum (RSFQ) digital systems. The circuits have only about 10-ps skew between input and output signals and are applicable for multirate digital systems (e,g., oversampling analog-to-digital converter and bit-serial digital systems). Several circuits have been fabricated in conventional Nb-trilayer technology with a critical current density of 1 kA/cm/sup 2/. The most complex clock controller generates trains of 2/sup 24/ single-flux-quantum pulses with a period of less than 70 ps. The long-term relative stability of these intervals has been measured to be better than 6/spl times/10/sup -5/. The basic component of the controller, a frequency divider, operates at input frequencies above 85 GHz.>
We have been developing a time-to-digital converter (TDC) using single-flux-quantum (SFQ) circuits in order to realize an imaging system based on a superconducting strip single-photon detector (SSPD). In this system, the absorption position of a single photon in a meander-shaped SSPD is determined by measuring the delay time of the detected signal propagating through an SSPD delay line. Increasing the time resolution of the TDC is the primary concern for improving the spatial resolution of the system. Here we focused on the double-oscillator SFQ TDC, where the difference of oscillation periods between two SFQ ring oscillators determines the time resolution. In the previous study, a time resolution of about 4 ps was demonstrated by using the Nb standard Josephson integrated circuit (IC) process with a critical current density of 2.5 kA/cm2. In this study, we improved the time resolution by adopting the Nb advanced Josephson IC process with a critical current density of 10 kA/cm2and by optimizing the circuit parameters of the coincidence detector. The histogram and the linearity of the delay measurements show that the time resolution is improved to up to 2 ps.
We have characterized Nb analog to digital converters using a resistor-coupled SFQ flip flop counter and a latching destructive readout (DRO). The counter used SFQ buffers between bits to provide isolation during destructive readout. We have measured parallel readout at sample rates up to 125 MSPS. We have also successfully operated an ADC which has Josephson junction regulated flip flop gate and readout bias busses. Using a self-resetting gate (SRG) at the carry out of the counter, we have measured the bit error rates (BER) of the counters. A two junction SQUID quantizer, biased in the voltage state, was used to produce correlated SFQ pulses at each junction. The SRG outputs of two 10 bit counters connected to the two quantizer outputs were compared. We measured a BER of /spl sim/5/spl times/10/sup -11/ with the quantizer operating at 19 GHz. We believe the principle error source is the latching SRG.
We designed and tested the digital readout circuitry for superconducting nanowire single-photon detectors (SNSPDs). The designed time-to-digital converter (TDC) comprises a decision-making block, a clock controller, and a counter with parallel-to-serial (P2S) interface. We also designed an on-chip pattern generator to imitate a digitized SNSPD response that allowed us to screen the circuitry without bonding actual SNSPDs. Both rapid single-flux quantum (RSFQ) and its energy-efficient rapid single-flux quantum (ERSFQ) versions were designed for comparison and debugging purposes. To optimize the design of the feeding Josephson transmission line (FJTL) required by the ERSFQ variant, we compared different power grid structures and types of FJTLs. Using an 8-bit counter with P2S interface as a device under test, we also investigated the effect of FJTL's size on the bias margins. FJTL with a 75% junction overhead is sufficient for the ERSFQ circuit to match the margins of its RSFQ counterpart. All chips have been fabricated at MIT-LL using the SFQ5ee process node. Experimental results and future research directions are presented.
Abstract An all-digital phase-locked loop (ADPLL) is a critical component for generating a precise clock sequence synchronized to a reference signal. For applications in superconducting qubit control, RSFQ ADPLL technology is promising due to its high-speed operation, low power consumption, and cryogenic compatibility. In this paper, we present the experimental validation of key elemental circuits for an improved RSFQ ADPLL: a digitally controlled oscillator (DCO), a time-to-digital converter (TDC), a buffer circuit in the proportional-differential (PD) controller, and a DCO controller. These test circuits were fabricated using a 10 kA/cm 2 Nb/AlO x /Nb process and characterized in a liquid helium bath. The experimental results demonstrated the successful operation of each circuit. Specifically, the DCO exhibited linear frequency control, and the TDC correctly generated digital signals according to the input time slots. The functional integrity of the PD controller’s buffer and the DCO controller was also confirmed. These results provide a foundation for the full integration of the RSFQ ADPLL.
Superconductive Rapid Single Flux Quantum (RSFQ) logic and memory, in which ones and zeros are represented by the presence or absence within a timing window of quantized picosecond voltage pulse (/spl int/v(t)dt=h/2e=2.07 mV/spl middot/ps), corresponding to one SFQ, can be integrated into a digital computing system with an operating rate of several tens of GHz, based on the present Nb Josephson junction integrated circuit technology. It is the most promising technology beyond semiconductor transistors for low-power high-end computation. However, as the operating speed of circuits and systems increase, timing uncertainty from fabrication process variations makes global synchronization very hard. In this paper, we present a globally asynchronous, locally synchronous timing methodology for RSFQ digital design, which can solve the global synchronization problem. We also demonstrate the recent experimental results of some asynchronous circuits and systems implemented in RSFQ technology. Several key components such as a self-timed shift register, a self-timed demultiplexor, a Muller-C element, a completion detector, and a clock generator have been designed and tested. High speed operation has been confirmed up to 20 Gb/s for a prototype data buffer system, which consists two self-timed shift registers and an on-chip 5-38 GHz clock generator.