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Journal of Physics Conference Series

Experimental Validation of Key Elemental Circuits for RSFQ All-Digital Phase Locked Loop

Yoshinao Mizugaki, Daiki Fukuyo

Published Jul 1, 2026• 0 citations
Publisher

Abstract

Abstract An all-digital phase-locked loop (ADPLL) is a critical component for generating a precise clock sequence synchronized to a reference signal. For applications in superconducting qubit control, RSFQ ADPLL technology is promising due to its high-speed operation, low power consumption, and cryogenic compatibility. In this paper, we present the experimental validation of key elemental circuits for an improved RSFQ ADPLL: a digitally controlled oscillator (DCO), a time-to-digital converter (TDC), a buffer circuit in the proportional-differential (PD) controller, and a DCO controller. These test circuits were fabricated using a 10 kA/cm 2 Nb/AlO x /Nb process and characterized in a liquid helium bath. The experimental results demonstrated the successful operation of each circuit. Specifically, the DCO exhibited linear frequency control, and the TDC correctly generated digital signals according to the input time slots. The functional integrity of the PD controller’s buffer and the DCO controller was also confirmed. These results provide a foundation for the full integration of the RSFQ ADPLL.

DOI
10.1088/1742-6596/3278/1/012022

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A low-skew frequency divider and clock controller have been designed for high-frequency timing of superconductor rapid single-flux-quantum (RSFQ) digital systems. The circuits have only about 10-ps skew between input and output signals and are applicable for multirate digital systems (e,g., oversampling analog-to-digital converter and bit-serial digital systems). Several circuits have been fabricated in conventional Nb-trilayer technology with a critical current density of 1 kA/cm/sup 2/. The most complex clock controller generates trains of 2/sup 24/ single-flux-quantum pulses with a period of less than 70 ps. The long-term relative stability of these intervals has been measured to be better than 6/spl times/10/sup -5/. The basic component of the controller, a frequency divider, operates at input frequencies above 85 GHz.>

IEEE Transactions on Applied Superconductivity•Jan 1, 1995•37 citations
Abstract An all-digital phase-locked loop (ADPLL) is a critical component for generating a precise clock sequence synchronized to a reference signal. For applications in superconducting qubit control, RSFQ ADPLL technology is promising due to its high-speed operation, low power consumption, and cryogenic compatibility. In this paper, we present the experimental validation of key elemental circuits for an improved RSFQ ADPLL: a digitally controlled oscillator (DCO), a time-to-digital converter (TDC), a buffer circuit in the proportional-differential (PD) controller, and a DCO controller. These test circuits were fabricated using a 10 kA/cm 2 Nb/AlO x /Nb process and characterized in a liquid helium bath. The experimental results demonstrated the successful operation of each circuit. Specifically, the DCO exhibited linear frequency control, and the TDC correctly generated digital signals according to the input time slots. The functional integrity of the PD controller’s buffer and the DCO controller was also confirmed. These results provide a foundation for the full integration of the RSFQ ADPLL.
Abstract This paper presents a new method for implementing an All-Digital Phase-Locked Loop (ADPLL) using rapid single flux quantum (RSFQ) circuit technology. The ADPLL consists of a digitally controlled oscillator (DCO), a time-to-digital converter (TDC), a proportional-differential (PD) controller, a DCO controller, and a frequency divider. The DCO is based on a ring oscillator with newly designed tunable delay Josephson transmission line (TDJTL) cells in series. Verilog simulations of the ADPLL demonstrate improved performance with the integration of the TDC and PD controller. In comparison with the configuration without the TDC, the new ADPLL configuration realizes a 54% reduction in the variation of the DCO oscillation period. This reduction in frequency variation makes the ADPLL particularly well-suited for applications requiring highly accurate frequency sources, such as transmon qubit control.
Superconductive Rapid Single Flux Quantum (RSFQ) logic and memory, in which ones and zeros are represented by the presence or absence within a timing window of quantized picosecond voltage pulse (/spl int/v(t)dt=h/2e=2.07 mV/spl middot/ps), corresponding to one SFQ, can be integrated into a digital computing system with an operating rate of several tens of GHz, based on the present Nb Josephson junction integrated circuit technology. It is the most promising technology beyond semiconductor transistors for low-power high-end computation. However, as the operating speed of circuits and systems increase, timing uncertainty from fabrication process variations makes global synchronization very hard. In this paper, we present a globally asynchronous, locally synchronous timing methodology for RSFQ digital design, which can solve the global synchronization problem. We also demonstrate the recent experimental results of some asynchronous circuits and systems implemented in RSFQ technology. Several key components such as a self-timed shift register, a self-timed demultiplexor, a Muller-C element, a completion detector, and a clock generator have been designed and tested. High speed operation has been confirmed up to 20 Gb/s for a prototype data buffer system, which consists two self-timed shift registers and an on-chip 5-38 GHz clock generator.
We have designed, fabricated, and successfully tested a Time-to-Digital converter (TDC). The TDC circuit consists of superconductive counters based on toggle flip-flops with destructive readout, shift registers, parallel-to-serial converters, and pulse detectors. The value of the counter is latched while the counter is operating at full speed. The TDC resolution is directly determined by the maximum counter speed, or 50 ps for an available 20 GHz clock rate. The circuits are implemented in HYPRES' standard Nb process with a critical current density of 1.0 kA/cm/sup 2/ using HYPRES' library of standard RSFQ cells.
Ring oscillators are the traditional on-chip clock source for RSFQ mixed-signal and digital circuits. Their long-term frequency stability is essential for certain signal processing applications such as the sampling clock for an A/D converter or the output clock of a D/A converter. However conventional bias schemes lead to excessive drift in the frequency. Embedding the ring oscillator in a phase-locked loop (PLL) circuit allows it to inherit the frequency stability of an external reference source. An RSFQ circuit comprised of a ring oscillator, a divide-by-2 20 prescaler and a resynchronizer D flip-flop was fabricated using the standard 1 kA cm -2 niobium foundry service from Hypres. The circuit was stabilized using a low-frequency PLL with a bandwidth of 6 Hz. The output of the phase detector in the PLL was used to produce a feedback current that stabilized the frequency of the ring oscillator at around 8 GHz. The frequency spectrum of the RSFQ scaled oscillator output was measured in open- and closed-loop configurations. Compared to the open-loop phase noise spectrum the closed-loop spectrum showed a decrease of 30 dB of the oscillator phase noise at an offset of 1 Hz from the divided-down carrier frequency of 4.1 kHz. This agreed with the classical phase-locked loop model for the system. The long-term frequency drift of the RSFQ clock was determined by the stability of the oven-controlled quartz oscillator used as the reference in the PLL.
AbstractSuperconducting digital technology based on Rapid Single Flux Quantum (RSFQ) logic offers a 50 times faster clock rate and 100 times less on chip power consumption than today's mainstream semiconductor electronics. This technology is attractive for many applications and in particular for Digital Signal Processing (DSP). The applications of the RSFQ DSPs are numerous and include multi-user detection in spread spectrum system, channel equalization for Multi-in, Multi-out (MIMO) systems, and blind detection and signal tracking for signal intelligence.At Chalmers we are developing a hybrid DSP with target performance of 30 giga operations per second. It consists of an RSFQ Multiply Accumulate unit (MAC), RSFQ fast cache memory, and an external semiconductor memory. The development of the complex high speed cryogenic digital system requires interface, packaging and testing solutions. The main difficulties are due to the 4 K operational temperature, the high magnetic field sensitivity of the RSFQ circuits, the multi-channel high bandwidth interface required in the hybrid architecture, and the high speed RSFQ digital core. The key steps towards addressing each of these problems are the subject of this thesis. The main emphasis is put on the experimental testing and interfacing of superconductor electronics. A large part of the work is connected to the experimental verification of DSP components and their incremental improvement towards functionality. The RSFQ circuits tested were fabricated using the four-metal layer VLSI processes available from NGST(8 kA/cm^2 Josephson junction critical current) and HYPRES (both 1 kA/cm^2 and HYPRES 4.5 kA/cm^2. The main results of the work are demonstrations of the RSFQ cache memory with more than 2,000 Josephson junctions, 33.5 GHz operation of the digital clock controller, and 20.48 GHz operation of the autocorrelator. In addition, various experiments have been done for investigation of parasitic effects in RSFQ circuits such as flux trapping and influence of the high current bias lines.At the final stage of the work, a unique high bandwidth 4 K cryocooler based experimental setup has been developed. The system, developed in close cooperation with Hypres Inc. USA, has 40 high speed I/Os with bandwidth of 2 Gbps, 64 DC bias channels, 4 high frequency clock lines, and 4 auxiliary control lines. It supports exchangeable test units for 10 mm x 10 mm and 20 mm x 20 mm Multi Chip Module (MCM) carriers. The availability of such a system is critical to demonstration of the hybrid DSP prototype and future commercialization.
A low-skew frequency divider and clock controller have been designed for high-frequency timing of superconductor rapid single-flux-quantum (RSFQ) digital systems. The circuits have only about 10-ps skew between input and output signals and are applicable for multirate digital systems (e,g., oversampling analog-to-digital converter and bit-serial digital systems). Several circuits have been fabricated in conventional Nb-trilayer technology with a critical current density of 1 kA/cm/sup 2/. The most complex clock controller generates trains of 2/sup 24/ single-flux-quantum pulses with a period of less than 70 ps. The long-term relative stability of these intervals has been measured to be better than 6/spl times/10/sup -5/. The basic component of the controller, a frequency divider, operates at input frequencies above 85 GHz.>