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Journal of Physics Conference Series

Design of an RSFQ All-Digital Phase Locked Loop with a Time-to-Digital Converter

Daiki Fukuyo, Hiroshi Shimada, Yoshinao Mizugaki

Published Jul 1, 2025• 0 citations
Publisher

Abstract

Abstract This paper presents a new method for implementing an All-Digital Phase-Locked Loop (ADPLL) using rapid single flux quantum (RSFQ) circuit technology. The ADPLL consists of a digitally controlled oscillator (DCO), a time-to-digital converter (TDC), a proportional-differential (PD) controller, a DCO controller, and a frequency divider. The DCO is based on a ring oscillator with newly designed tunable delay Josephson transmission line (TDJTL) cells in series. Verilog simulations of the ADPLL demonstrate improved performance with the integration of the TDC and PD controller. In comparison with the configuration without the TDC, the new ADPLL configuration realizes a 54% reduction in the variation of the DCO oscillation period. This reduction in frequency variation makes the ADPLL particularly well-suited for applications requiring highly accurate frequency sources, such as transmon qubit control.

DOI
10.1088/1742-6596/3054/1/012024

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IEEE Transactions on Applied Superconductivity•Jun 1, 1999•46 citations
Abstract This paper presents a new method for implementing an All-Digital Phase-Locked Loop (ADPLL) using rapid single flux quantum (RSFQ) circuit technology. The ADPLL consists of a digitally controlled oscillator (DCO), a time-to-digital converter (TDC), a proportional-differential (PD) controller, a DCO controller, and a frequency divider. The DCO is based on a ring oscillator with newly designed tunable delay Josephson transmission line (TDJTL) cells in series. Verilog simulations of the ADPLL demonstrate improved performance with the integration of the TDC and PD controller. In comparison with the configuration without the TDC, the new ADPLL configuration realizes a 54% reduction in the variation of the DCO oscillation period. This reduction in frequency variation makes the ADPLL particularly well-suited for applications requiring highly accurate frequency sources, such as transmon qubit control.
Abstract An all-digital phase-locked loop (ADPLL) is a critical component for generating a precise clock sequence synchronized to a reference signal. For applications in superconducting qubit control, RSFQ ADPLL technology is promising due to its high-speed operation, low power consumption, and cryogenic compatibility. In this paper, we present the experimental validation of key elemental circuits for an improved RSFQ ADPLL: a digitally controlled oscillator (DCO), a time-to-digital converter (TDC), a buffer circuit in the proportional-differential (PD) controller, and a DCO controller. These test circuits were fabricated using a 10 kA/cm 2 Nb/AlO x /Nb process and characterized in a liquid helium bath. The experimental results demonstrated the successful operation of each circuit. Specifically, the DCO exhibited linear frequency control, and the TDC correctly generated digital signals according to the input time slots. The functional integrity of the PD controller’s buffer and the DCO controller was also confirmed. These results provide a foundation for the full integration of the RSFQ ADPLL.
Ring oscillators are the traditional on-chip clock source for RSFQ mixed-signal and digital circuits. Their long-term frequency stability is essential for certain signal processing applications such as the sampling clock for an A/D converter or the output clock of a D/A converter. However conventional bias schemes lead to excessive drift in the frequency. Embedding the ring oscillator in a phase-locked loop (PLL) circuit allows it to inherit the frequency stability of an external reference source. An RSFQ circuit comprised of a ring oscillator, a divide-by-2 20 prescaler and a resynchronizer D flip-flop was fabricated using the standard 1 kA cm -2 niobium foundry service from Hypres. The circuit was stabilized using a low-frequency PLL with a bandwidth of 6 Hz. The output of the phase detector in the PLL was used to produce a feedback current that stabilized the frequency of the ring oscillator at around 8 GHz. The frequency spectrum of the RSFQ scaled oscillator output was measured in open- and closed-loop configurations. Compared to the open-loop phase noise spectrum the closed-loop spectrum showed a decrease of 30 dB of the oscillator phase noise at an offset of 1 Hz from the divided-down carrier frequency of 4.1 kHz. This agreed with the classical phase-locked loop model for the system. The long-term frequency drift of the RSFQ clock was determined by the stability of the oven-controlled quartz oscillator used as the reference in the PLL.
HYPRES has developed a monolithic on-chip phase-locked loop (PLL) for the stabilizing and locking of the high-frequency output of an single flux quantum (SFQ) clock source, using rapid single flux quantum (RSFQ) logic family elements for phase detection and frequency detection. This PLL was successfully fabricated and operated as a 50 GHz clock phase-locked to a MHz frequency external source. We were able to employ a feedback loop filter to correct the voltage bias on the SFQ clock and compensate for the frequency fluctuations created by voltage noise in the bias and shunt resistors. This effort resulted is a stable SFQ clock which is tunable and phase-locked to an external signal of lower frequency, and which does not increase the heat load of a circuit. Moreover, in addition to high speed synchronized clock sources, this PLL can now be used to implement new and useful devices, such as phase demodulators and clock recovery circuits.
We present a technique for linewidth measurement and phase-locking of Josephson oscillators using digital rapid single-flux-quantum (RSFQ) circuits. The oscillator consists of a resistively shunted 6 /spl mu/m/spl times/6 /spl mu/m Nb/AlO/sub x//Nb Josephson tunnel junction that is integrated with RSFQ input and output circuits. A cascade of RSFQ T flip-flops is used to directly monitor the output of the Josephson oscillator. Spectral characteristics have been measured directly for oscillator frequencies ranging from 10-50 GHz. The linewidth can be reduced by over 100 times by phase-locking the oscillator to an RSFQ pulse train generated by an external sinusoidal signal. These Josephson oscillators can be used as on-chip stable high frequency clocks for RSFQ circuits.
A low-skew frequency divider and clock controller have been designed for high-frequency timing of superconductor rapid single-flux-quantum (RSFQ) digital systems. The circuits have only about 10-ps skew between input and output signals and are applicable for multirate digital systems (e,g., oversampling analog-to-digital converter and bit-serial digital systems). Several circuits have been fabricated in conventional Nb-trilayer technology with a critical current density of 1 kA/cm/sup 2/. The most complex clock controller generates trains of 2/sup 24/ single-flux-quantum pulses with a period of less than 70 ps. The long-term relative stability of these intervals has been measured to be better than 6/spl times/10/sup -5/. The basic component of the controller, a frequency divider, operates at input frequencies above 85 GHz.>
Digital to analog converters based on the Josephson effect are promising for voltage standards, because they produce voltage steps with ultimate precision and stability. In this paper, we describe a project to develop a Josephson D/A converter designed for synthesizing a sinusoidal waveform with metrological accuracy. The D/A converter is based on RSFQ (Rapid Single Flux Quantum) logic circuits, and consists of a frequency multiplier (FM), a pulse distributor (PD), and a number of voltage multipliers (VMs). Each VM circuit, corresponding to the n-th bit digital code, multiplies the number of SFQ pulses by a factor of 2/sup n/. By gating the input SFQ pulses from the FM to the VMs using the PD circuits, a programmable output voltage is obtained. Possible sources of uncertainties in the measurement of the rms value of the synthesized sine wave are discussed.