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IEEE Transactions on Applied Superconductivity

Low-Power Digital Readout Circuit for Superconductor Nanowire Single-Photon Detectors

Anubhav Sahu, M. Celik, Dmitri E. Kirichenko, Timur V. Filippov, Deepnarayan Gupta

Published Mar 18, 2019• 17 citations
Publisher

Abstract

We designed and tested the digital readout circuitry for superconducting nanowire single-photon detectors (SNSPDs). The designed time-to-digital converter (TDC) comprises a decision-making block, a clock controller, and a counter with parallel-to-serial (P2S) interface. We also designed an on-chip pattern generator to imitate a digitized SNSPD response that allowed us to screen the circuitry without bonding actual SNSPDs. Both rapid single-flux quantum (RSFQ) and its energy-efficient rapid single-flux quantum (ERSFQ) versions were designed for comparison and debugging purposes. To optimize the design of the feeding Josephson transmission line (FJTL) required by the ERSFQ variant, we compared different power grid structures and types of FJTLs. Using an 8-bit counter with P2S interface as a device under test, we also investigated the effect of FJTL's size on the bias margins. FJTL with a 75% junction overhead is sufficient for the ERSFQ circuit to match the margins of its RSFQ counterpart. All chips have been fabricated at MIT-LL using the SFQ5ee process node. Experimental results and future research directions are presented.

DOI
10.1109/tasc.2019.2895051

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We demonstrate the transfer of single photon triggered electrical pulses from a superconducting nanowire single photon detector (SNSPD) to a single flux quantum (SFQ) pulse. We describe design and test of a digital SFQ based SNSPD readout circuit and demonstrate its correct operation. Both circuits (SNSPD and SFQ) operate under the same cryogenic conditions and are directly connected by wire bonds. A future integration of the present multi-chip configuration seems feasible because both fabrication process and materials are very similar. In contrast to commonly used semiconductor amplifiers, SFQ circuits combine very low power dissipation (a few microwatts) with very high operation speed, thus enabling count-rates of several gigahertz. The SFQ interface circuit simplifies the SNSPD readout and enables large numbers of detectors for future compact multi-pixel systems with single photon counting resolution. The demonstrated circuit has great potential for scaling the present interface solution to 1,000 detectors by using a single SFQ chip.
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We propose an efficient multiplexing technique for superconducting nanowire single-photon detectors based on an orthogonal detector bias switching method enabling the extraction of the average count rate of a set of detectors by one readout line. We implemented a system prototype where the SNSPDs are connected to an integrated cryogenic readout and a pulse merger system based on rapid single flux quantum (RSFQ) electronics. We discuss the general scalability of this concept, analyze the environmental requirements which define the resolvability and the accuracy and demonstrate the feasibility of this approach with experimental results for a SNSPD array with four pixels.
The Energy-efficient Rapid Single Flux Quantum (ERSFQ) logic family offers zero-static power dissipation. Any ERSFQ circuit requires a feeding Josephson transmission line (FJTL), a relatively large active transmission line, which serves as an accurate voltage source. For proper operation, the FJTL needs to be continuously pumped at a frequency that is equal to or higher than the highest clock frequency of the ERSFQ circuit. We selected an on-chip pseudo-random binary sequence (PRBS) generator as the example circuit since it naturally facilitates quantitative measurements of operating bias margins in terms of bit error rate (BER). Using external and internal flux pump sources, we performed extensive experimental studies on BER for ERSFQ PRBS generators operating at clock frequencies up to 50 GHz. We paid special attention to the over-pumping regime, where the FJTL pump frequency is higher than the PRBS clock frequency and confirmed its superiority in improving BER. At 35.56 GHz clock frequency, a group of 4 PRBS generators and 4 individual FJTLs with the bias current ratio (BCR) equal to 1, had a BER lower than 10−12and bias margins of ±25% for internal and external flux pump sources over-pumping at 6.25% above clock frequency. The maximal operational clock frequency of a single ERSFQ PRBS generator with intrinsic pump source (+6.25% over-pumping) and BER−12was 49.53 GHz. We also focused on optimization of the FJTL's size to reduce the power consumption and the area occupied by the FJTL itself. All chips were fabricated at MIT-Lincoln Laboratory using the SFQ5ee fab node. Future steps required for better understanding of ERSFQ operation are discussed.