Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

Journal of Physics Conference Series

Universal asynchronous RSFQ gate for realization of Boolean functions of dual-rail binary variables

Boyko Dimov, M. Khabipov, D Balashov, C.M. Brandt, Thomas Ortlepp, Daniel Hagedorn, F-Im Buchholz, J. Niemeyer, Friedrich Uhlmann

Published Jun 1, 2006• 4 citations
Publisher

Abstract

We report on the design, optimization, fabrication, and successful testing of an universal asynchronous RSFQ logic gate based on the dual-rail data coding. Properly connecting its inputs and outputs, one can perform most of the basic Boolean functions over a pair of dual-rail input variables. Therefore, this gate is fundamental component for the development of high-speed complex asynchronous RSFQ digital devices.

DOI
10.1088/1742-6596/43/1/288

Related papers

Rapid single-flux-quantum dual-rail logic for asynchronous circuits

Masaaki Maezawa, I. Kurosawa, Masahiro Aoyagi +3 more

Dual-rail logic circuit elements based on rapid single-flux-quantum (RSFQ) technology have been designed and simulated. The proposed circuits can operate asynchronously, since dual-rail data include timing information in themselves. Therefore dual-rail logic scheme has a possibility of solving some problems of RSFQ circuits with flow clocking, which would become more serious as operating speed and complexity of the circuit increase. Implementation of RSFQ dual-rail AND and XOR cells is described. A scheme of transfer-ring data from a flow-clocked circuit to a parallel dual-rail circuit is also proposed, which a fully asynchronous dual-rail demultiplexer.

IEEE Transactions on Applied Superconductivity•Jun 1, 1997•31 citations

Pulse-driven dual-rail logic gate family based on rapid single-flux-quantum (RSFQ) devices for asynchronous circuits

Masaaki Maezawa, I. Kurosawa, Y. Kameda +1 more

We present a pulse-driven asynchronous logic gate family based on a high-speed, low-power Josephson-junction device of rapid single-flux-quantum (RSFQ) circuits. Dual-rail logic is used and clock-free operation is realized. The proper operation of the circuits is confirmed by the numerical simulation which shows logic delays are about 60 ps for an AND and about 80 ps for an XOR. Power consumption is estimated to be 10 /spl mu/W/gate.

IEEE International Symposium on Asynchronous Circuits and Systems (ASYNC)•Dec 23, 2002•17 citations

Dual-Rail Asynchronous Quantum Phase-Slip Logic Gates

Babak Dastbarjan Boroujeni, Seyed Amir Hashemi, Satyabrata Jit

Superconducting logic gates need synchronization clock in order to synchronize the inputs for performing the Boolean functions properly; i.e. the inputs should arrive to the gate and the output is valid when the clock is in the high state. However, for large scale circuits, large clock routes impose limits on circuit design, such as clock skew, narrow timing tolerances, synchronization violation and system integrity. Dual-rail topology for asynchronous logic circuit design overcomes these limits to a satisfactory level, by eliminating the clocking routes and producing local clock pulses. In this manuscript, design of the dual-rail asynchronous logic gates (AND, OR and XOR) based on the superconducting quantum phase slip (QPS) is represented. As the dual-rail topology adds extra elements to the final circuit, in order to reduce the total number of elements, first, the timed QPS AND, OR and XOR gates, splitter, confluence buffer and coincidence junction with reduced number of elements are designed. Then these elements are used to design the corresponding final dual-rail asynchronous QPS gates. Proper operation of the proposed asynchronous gates are investigated by simulation results. Finally, delay analysis is provided in order to estimate operation frequency limit of the proposed asynchronous gates.

IEEE Transactions on Applied Superconductivity•May 6, 2025•1 citation

An asynchronous rapid single-flux-quantum demultiplexer based on dual-rail information coding

Boyko Dimov, M. Khabipov, D Balashov +4 more

We present a novel asynchronous RSFQ demultiplexer based on dual-rail information coding. The electrical scheme of the circuit is designed and optimized to maximize the margins of its elements and to improve the fabrication yield. This optimized scheme has been fabricated with the 4 µm 1 kA cm−2 Nb/Al2O3–Al/Nb technology of PTB-Braunschweig. The demultiplexer has been tested with different samples of the low-speed incoming data stream and in all cases a correct circuit functionality has been observed.

Superconductor Science and Technology•Apr 5, 2005•1 citation

Novel dual-rail gates structure and their application in 1-bit-full-adder

Lei Wang, Boran Guan

Superconductive rapid single flux quantum (RSFQ) digital computing system has the tendency to achieve the operating rate of several hundred GHz. Compare to the semiconductor partner, with the pulse width about picoseconds and clock rate of several hundred GHz, the timing uncertainty from fabrication process variations makes it impossible to achieve the large scale integrated chip with global synchronization architecture. Many efforts, in this field, have been made to construct the asynchronous RSFQ timing conformation with advanced performances. In this paper, a novel AND gate and a novel universal gate based on dual-rail methodology are proposed. The new gates have the advantages in less Josephson junction count and less signal time delay over the previous published version. A 1-bit-full-adder has been implemented based on the novel gates, the simulation shows that they function well and can be considered as the candidates in the system construction. Furthermore, the properties of the gates circuits have also been analyzed numerically with its sensitivity for parameters and tolerant for margin error.

International Conference on Applied Superconductivity and Electromagnetic Devices•Sep 1, 2009•0 citations

Optimised asynchronous self-timing for superconducting RSFQ logic circuits

H.R. Gerber, Coenrad Johann Fourie, Willem Jakobus Perold

Rapid single flux quantum (RSFQ) logic is a digital circuit technology that in recent years has presented itself as an alternative to semiconductors in the application of ultra high speed, very low power applications. The optimal timing of digital circuits operating at hundreds of GHz is still a complex problem for both RSFQ and semiconductor technologies. The fact that most RSFQ gates require a clock signal to function makes this even more complex. Various RSFQ timing schemes have been adapted from semiconductor design methodologies, and some have been designed specifically for RSFQ. Currently, synchronous clocking schemes outperform other schemes, but with the scale of RSFQ circuits ever increasing, the proper use of timing schemes are becoming more crucial. This paper describes a new asynchronous self-timing scheme where the details of clock distribution and clocking are built into the logic gates. Tests were done on the newly developed asynchronous logic gates and an asynchronous full adder was implemented and tested

IEEE AFRICON•Apr 6, 2005•2 citations
We report on the design, optimization, fabrication, and successful testing of an universal asynchronous RSFQ logic gate based on the dual-rail data coding. Properly connecting its inputs and outputs, one can perform most of the basic Boolean functions over a pair of dual-rail input variables. Therefore, this gate is fundamental component for the development of high-speed complex asynchronous RSFQ digital devices.
Dual-rail logic circuit elements based on rapid single-flux-quantum (RSFQ) technology have been designed and simulated. The proposed circuits can operate asynchronously, since dual-rail data include timing information in themselves. Therefore dual-rail logic scheme has a possibility of solving some problems of RSFQ circuits with flow clocking, which would become more serious as operating speed and complexity of the circuit increase. Implementation of RSFQ dual-rail AND and XOR cells is described. A scheme of transfer-ring data from a flow-clocked circuit to a parallel dual-rail circuit is also proposed, which a fully asynchronous dual-rail demultiplexer.
Superconducting logic gates need synchronization clock in order to synchronize the inputs for performing the Boolean functions properly; i.e. the inputs should arrive to the gate and the output is valid when the clock is in the high state. However, for large scale circuits, large clock routes impose limits on circuit design, such as clock skew, narrow timing tolerances, synchronization violation and system integrity. Dual-rail topology for asynchronous logic circuit design overcomes these limits to a satisfactory level, by eliminating the clocking routes and producing local clock pulses. In this manuscript, design of the dual-rail asynchronous logic gates (AND, OR and XOR) based on the superconducting quantum phase slip (QPS) is represented. As the dual-rail topology adds extra elements to the final circuit, in order to reduce the total number of elements, first, the timed QPS AND, OR and XOR gates, splitter, confluence buffer and coincidence junction with reduced number of elements are designed. Then these elements are used to design the corresponding final dual-rail asynchronous QPS gates. Proper operation of the proposed asynchronous gates are investigated by simulation results. Finally, delay analysis is provided in order to estimate operation frequency limit of the proposed asynchronous gates.
We present a novel asynchronous RSFQ demultiplexer based on dual-rail information coding. The electrical scheme of the circuit is designed and optimized to maximize the margins of its elements and to improve the fabrication yield. This optimized scheme has been fabricated with the 4 µm 1 kA cm−2 Nb/Al2O3–Al/Nb technology of PTB-Braunschweig. The demultiplexer has been tested with different samples of the low-speed incoming data stream and in all cases a correct circuit functionality has been observed.
Superconductive rapid single flux quantum (RSFQ) digital computing system has the tendency to achieve the operating rate of several hundred GHz. Compare to the semiconductor partner, with the pulse width about picoseconds and clock rate of several hundred GHz, the timing uncertainty from fabrication process variations makes it impossible to achieve the large scale integrated chip with global synchronization architecture. Many efforts, in this field, have been made to construct the asynchronous RSFQ timing conformation with advanced performances. In this paper, a novel AND gate and a novel universal gate based on dual-rail methodology are proposed. The new gates have the advantages in less Josephson junction count and less signal time delay over the previous published version. A 1-bit-full-adder has been implemented based on the novel gates, the simulation shows that they function well and can be considered as the candidates in the system construction. Furthermore, the properties of the gates circuits have also been analyzed numerically with its sensitivity for parameters and tolerant for margin error.
Rapid single flux quantum (RSFQ) logic is a digital circuit technology that in recent years has presented itself as an alternative to semiconductors in the application of ultra high speed, very low power applications. The optimal timing of digital circuits operating at hundreds of GHz is still a complex problem for both RSFQ and semiconductor technologies. The fact that most RSFQ gates require a clock signal to function makes this even more complex. Various RSFQ timing schemes have been adapted from semiconductor design methodologies, and some have been designed specifically for RSFQ. Currently, synchronous clocking schemes outperform other schemes, but with the scale of RSFQ circuits ever increasing, the proper use of timing schemes are becoming more crucial. This paper describes a new asynchronous self-timing scheme where the details of clock distribution and clocking are built into the logic gates. Tests were done on the newly developed asynchronous logic gates and an asynchronous full adder was implemented and tested