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IEEE Transactions on Applied Superconductivity

Dual-Rail Asynchronous Quantum Phase-Slip Logic Gates

Babak Dastbarjan Boroujeni, Seyed Amir Hashemi, Satyabrata Jit

Published May 6, 2025• 1 citation
Publisher

Abstract

Superconducting logic gates need synchronization clock in order to synchronize the inputs for performing the Boolean functions properly; i.e. the inputs should arrive to the gate and the output is valid when the clock is in the high state. However, for large scale circuits, large clock routes impose limits on circuit design, such as clock skew, narrow timing tolerances, synchronization violation and system integrity. Dual-rail topology for asynchronous logic circuit design overcomes these limits to a satisfactory level, by eliminating the clocking routes and producing local clock pulses. In this manuscript, design of the dual-rail asynchronous logic gates (AND, OR and XOR) based on the superconducting quantum phase slip (QPS) is represented. As the dual-rail topology adds extra elements to the final circuit, in order to reduce the total number of elements, first, the timed QPS AND, OR and XOR gates, splitter, confluence buffer and coincidence junction with reduced number of elements are designed. Then these elements are used to design the corresponding final dual-rail asynchronous QPS gates. Proper operation of the proposed asynchronous gates are investigated by simulation results. Finally, delay analysis is provided in order to estimate operation frequency limit of the proposed asynchronous gates.

DOI
10.1109/tasc.2025.3567466

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Superconducting logic gates need synchronization clock in order to synchronize the inputs for performing the Boolean functions properly; i.e. the inputs should arrive to the gate and the output is valid when the clock is in the high state. However, for large scale circuits, large clock routes impose limits on circuit design, such as clock skew, narrow timing tolerances, synchronization violation and system integrity. Dual-rail topology for asynchronous logic circuit design overcomes these limits to a satisfactory level, by eliminating the clocking routes and producing local clock pulses. In this manuscript, design of the dual-rail asynchronous logic gates (AND, OR and XOR) based on the superconducting quantum phase slip (QPS) is represented. As the dual-rail topology adds extra elements to the final circuit, in order to reduce the total number of elements, first, the timed QPS AND, OR and XOR gates, splitter, confluence buffer and coincidence junction with reduced number of elements are designed. Then these elements are used to design the corresponding final dual-rail asynchronous QPS gates. Proper operation of the proposed asynchronous gates are investigated by simulation results. Finally, delay analysis is provided in order to estimate operation frequency limit of the proposed asynchronous gates.
In this article, clockless circuits of the two basic logic gates, namely,andandorgates, are designed using the quantum phase slip junction (QPSJ). In the previously designed (existing) circuits of these gates, there is an internal clock pulse source in the output branch, which is necessary for proper gate operation. When the existingandandorgates have to be connected to another gate, this internal clock pulse becomes a series between their outputs and the input of the next gate. As a result, the internal clock pulse must be provided by a separate source, but synchronized to the system clock pulse (which is needed for synchronization of the inputs). This increases the design complexity. By using the proposed clocklessandandorgates, the mentioned design complexity is removed. In addition, the proposed clockless gates have less number of QPSJs than the existing ones, which allows less occupied area on the chip, a higher operation frequency, and smaller dynamic power dissipation.
Dual-rail logic circuit elements based on rapid single-flux-quantum (RSFQ) technology have been designed and simulated. The proposed circuits can operate asynchronously, since dual-rail data include timing information in themselves. Therefore dual-rail logic scheme has a possibility of solving some problems of RSFQ circuits with flow clocking, which would become more serious as operating speed and complexity of the circuit increase. Implementation of RSFQ dual-rail AND and XOR cells is described. A scheme of transfer-ring data from a flow-clocked circuit to a parallel dual-rail circuit is also proposed, which a fully asynchronous dual-rail demultiplexer.
Quantum phase slip (QPS) junction can act as a superconductor switch when a voltage pulse larger than its critical voltage is applied to it. As a result, a current pulse with an area equal to 2e(or multiples of 2e) flows across the junction, and the junction switches from zero to one in the charge-base logic. For having a proper operation simulation of the QPS junction, it should be overdamped, and the damping factor should be less than one. Physical parameters of the QPS junction, namely, the normal resistance, the kinetic inductance, and the critical voltage, can affect the overdamping condition and switching behavior of the junction, as well as the damping factor. The basic block for designing the QPS logic gates is the charge island. By different and proper connections of the charge islands, basic QPSand, or, andxorlogic gates are designed. Generally, each of these gates has its own circuit and junction parameters for proper operation. In this manuscript, a universal QPS logic gate is proposed that can perform basicand, or, andxorBoolean functions by proper selection of parameters for QPS junctions in the case of each Boolean function. This universal QPS logic gate can simplify the design the complicated QPS logic circuits, since only the parameters of each junction have to be properly selected for achieving the desired Boolean function, and the gate circuit topology remains unchanged.
Although superconducting single flux quantum (SFQ) technologies offer the potential for low-latency operation with energy dissipation of the order of attojoules per gate, their inherently pulse-driven nature and stateful cells have led to designs in which every logic gate is clocked. This means that clocked buffers must be added to equalize logic path lengths, and every gate becomes a pipeline stage. We propose a different approach, where gates are clock-free and synchronous designs have a conventional look-and-feel. Despite being clock-free, however, the gates are state machines by nature. To properly manage these state machines, the logical clock cycle is composed of two synchronous alternating phases: the first of which implements the desired function, and the second of which returns the state machines to the ground state. Moreover, to address the challenges associated with the asynchronous implementation of Boolean NOT operations in pulse-based systems, values are represented as unordered binary codes – in particular, dual-rail codes. With unordered codes, AND and OR operations are functionally complete.We demonstrate that our new approach, xSFQ, with its dual-rail construction and alternating clock phases, along with "double-pumped" logical latches and a timing optimization through latch decomposition, is capable of implementing arbitrary digital designs without gate-level pipelining and the overheads that come with it. We evaluate energy-delay trade-offs enabled by this approach through a mix of detailed analog circuit modeling, pulse-level discrete-event simulation, and high-level pipeline efficiency analysis. The resulting systems are shown to deliver energy-delay product (EDP) gains over conventional SFQ even with pipeline hazard ratios (HR) below 1%. For hazard ratios equal to 15% and 20% and a design resembling a RISC-V RV32I core (excluding the cost of interlock logic), xSFQ achieves 22x and 31x EDP savings, respectively.
In this article, the quantum phase slip junction (QPSJ) based full adder, multiplexer, and demultiplexer memoryless circuits for superconducting digital applications are designed for the first time. Generally, the memoryless circuits are implemented by interconnection of the basic gates (i.e., AND, OR, NOT). So in this article, the structures of the QPSJ-based AND and OR gates are also modified in order to reduce the complexity of their connections to the other gates by removing or changing the location of the clock pulse from their output branches. When a gate is connected to the next one, the elements of the second gate are loaded to the circuit of the first gate. The output current of the first gate will be affected due to this loading and no Cooper pair may be produced at its output and the next connected gate will not be switched. Therefore, the main tip in designing of these circuits is that each constituent gate must provide the necessary output current to drive the next connected gates, since each gate is driven by one Cooper pair. In this article, providing sufficient output current for each gate has been observed by 1) selecting proper critical voltages of the QPSJs and 2) by adding extra elements to or removing some elements from the connected gates in the proposed memoryless circuits.