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Proceedings - International Symposium on Computer Architecture/Proceedings

Superconducting Computing with Alternating Logic Elements

Georgios Tzimpragos, Jennifer E. Volk, Alex Wynn, James Edward Smith, Timothy Sherwood

Published Jun 1, 2021• 21 citations
Publisher

Abstract

Although superconducting single flux quantum (SFQ) technologies offer the potential for low-latency operation with energy dissipation of the order of attojoules per gate, their inherently pulse-driven nature and stateful cells have led to designs in which every logic gate is clocked. This means that clocked buffers must be added to equalize logic path lengths, and every gate becomes a pipeline stage. We propose a different approach, where gates are clock-free and synchronous designs have a conventional look-and-feel. Despite being clock-free, however, the gates are state machines by nature. To properly manage these state machines, the logical clock cycle is composed of two synchronous alternating phases: the first of which implements the desired function, and the second of which returns the state machines to the ground state. Moreover, to address the challenges associated with the asynchronous implementation of Boolean NOT operations in pulse-based systems, values are represented as unordered binary codes – in particular, dual-rail codes. With unordered codes, AND and OR operations are functionally complete.We demonstrate that our new approach, xSFQ, with its dual-rail construction and alternating clock phases, along with "double-pumped" logical latches and a timing optimization through latch decomposition, is capable of implementing arbitrary digital designs without gate-level pipelining and the overheads that come with it. We evaluate energy-delay trade-offs enabled by this approach through a mix of detailed analog circuit modeling, pulse-level discrete-event simulation, and high-level pipeline efficiency analysis. The resulting systems are shown to deliver energy-delay product (EDP) gains over conventional SFQ even with pipeline hazard ratios (HR) below 1%. For hazard ratios equal to 15% and 20% and a design resembling a RISC-V RV32I core (excluding the cost of interlock logic), xSFQ achieves 22x and 31x EDP savings, respectively.

DOI
10.1109/isca52012.2021.00057

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Although superconducting single flux quantum (SFQ) technologies offer the potential for low-latency operation with energy dissipation of the order of attojoules per gate, their inherently pulse-driven nature and stateful cells have led to designs in which every logic gate is clocked. This means that clocked buffers must be added to equalize logic path lengths, and every gate becomes a pipeline stage. We propose a different approach, where gates are clock-free and synchronous designs have a conventional look-and-feel. Despite being clock-free, however, the gates are state machines by nature. To properly manage these state machines, the logical clock cycle is composed of two synchronous alternating phases: the first of which implements the desired function, and the second of which returns the state machines to the ground state. Moreover, to address the challenges associated with the asynchronous implementation of Boolean NOT operations in pulse-based systems, values are represented as unordered binary codes – in particular, dual-rail codes. With unordered codes, AND and OR operations are functionally complete.We demonstrate that our new approach, xSFQ, with its dual-rail construction and alternating clock phases, along with "double-pumped" logical latches and a timing optimization through latch decomposition, is capable of implementing arbitrary digital designs without gate-level pipelining and the overheads that come with it. We evaluate energy-delay trade-offs enabled by this approach through a mix of detailed analog circuit modeling, pulse-level discrete-event simulation, and high-level pipeline efficiency analysis. The resulting systems are shown to deliver energy-delay product (EDP) gains over conventional SFQ even with pipeline hazard ratios (HR) below 1%. For hazard ratios equal to 15% and 20% and a design resembling a RISC-V RV32I core (excluding the cost of interlock logic), xSFQ achieves 22x and 31x EDP savings, respectively.
Superconductive electronics is a promising candidate for supplementing or replacing existing CMOS VLSI systems. Rapid single-flux quantum (RSFQ) is one of the most advanced superconductive technologies operating at tens of gigahertz while reducing the operating power by up to three orders of magnitude as compared to conventional semiconductor systems. Achieving VLSI complexity of RSFQ integrated systems, however remains an elusive task due to fundamental differences between RSFQ and CMOS technologies. Most RSFQ logic gates, such as NOT and XOR are sequential in nature. Compared to CMOS, the number of logical pipeline stages is prohibitively large, greatly complicating the design of complex systems. Furthermore, additional circuitry, such as splitters and path balancing flip flops, constitute a major overhead. In this paper, a gate compounding technique is presented to maximize the functionality achievable within a single clock cycle. The logic gates are decomposed into primitives that can be efficiently combined to evaluate complex expressions in a single clock cycle. Structures generated by gate compounding are not sensitive to signal arrival time, simplifying the system design process. The expressive power of SFQ logic is increased, allowing any two-input truth table to be implemented within a single clock cycle. A 4-bit carry lookahead adder (CLA) is implemented using compound gates, demonstrating smaller area, pipeline depth, and clock tree size.
Superconducting logic gates need synchronization clock in order to synchronize the inputs for performing the Boolean functions properly; i.e. the inputs should arrive to the gate and the output is valid when the clock is in the high state. However, for large scale circuits, large clock routes impose limits on circuit design, such as clock skew, narrow timing tolerances, synchronization violation and system integrity. Dual-rail topology for asynchronous logic circuit design overcomes these limits to a satisfactory level, by eliminating the clocking routes and producing local clock pulses. In this manuscript, design of the dual-rail asynchronous logic gates (AND, OR and XOR) based on the superconducting quantum phase slip (QPS) is represented. As the dual-rail topology adds extra elements to the final circuit, in order to reduce the total number of elements, first, the timed QPS AND, OR and XOR gates, splitter, confluence buffer and coincidence junction with reduced number of elements are designed. Then these elements are used to design the corresponding final dual-rail asynchronous QPS gates. Proper operation of the proposed asynchronous gates are investigated by simulation results. Finally, delay analysis is provided in order to estimate operation frequency limit of the proposed asynchronous gates.
This paper presents a basic circuit concept for pulse-driven asynchronous circuits using superconducting rapid single-flux-quantum (RSFQ) logic gates. Today's computer systems perform using a synchronous clock distributed over the whole system. The distribution of the clock signal becomes more difficult as the clock frequency increases because the wavelength of the clock signal becomes shorter than the system size. One way to solve this problem is to use asynchronous circuits in which all circuits perform their functions only under the law of cause and effect. We propose an implementation of the basic asynchronous circuit performing OR/AND logic operations between SFQ pulses. The operations are confirmed by SPICE simulation. We will show a design method for combinational circuits using the proposed basic circuits.
An architecture of rapid single-flux-quantum logic circuits using clockless gates is proposed. Compared with a circuit composed of only clocked gates, a circuit using clockless gates includes fewer clocked gates, and therefore, a smaller clock distribution network. A circuit in the proposed architecture is constructed from pipeline stages. Each pipeline stage consists of a column of clocked gates and a succeeding block of clockless gates. The function of a pipeline register of a stage is implemented by the latching function of the clocked gates in the column. The combinational logic of a stage is implemented by the logic function of the clocked gates in the column and that of the clockless gates in the block. We designed a two-stage-pipelined 4-bit carry-lookahead-adder using clockless gates as a design example of the proposed architecture. It had reductions of the count of clocked gates and the area by 33 and 13%, respectively, compared with that composed of only clocked gates. The 4-bit adder in the proposed architecture was fabricated and demonstrated with the maximum clock frequency of 21.4 GHz and the bias margin of ±16%.
Quantum electronic circuits where the logic information is processed and stored in single flux quanta promise efficient computation in a performance/power metric, and thus are of utmost interest as possible replacement or enhancement of CMOS. Several electronic device families leverage superconducting materials and transitions between resistive and superconducting states. Information is coded into bits with deterministic values - as opposed to qubits used in quantum computing. As an example, information can be coded into pulses. Logic gates can be modeled as finite-state machines, that emit logic outputs in response to inputs. The most natural realization of such circuits is through synchronous implementations, where a clock stimulus is transmitted to every logic gate and where logic depth is balanced at every input to achieve full synchrony. Novel superconducting realization families try to go beyond the limitations of synchronous logic with approaches reminiscent of asynchronous design style and leveraging information coding. Moreover, some superconducting families exploit adiabatic operation, in the search for minimizing energy consumption. Design automation for quantum electronic logic families is still in its infancy, but important results have been achieved in terms of automatic balancing and fanout management. The combination of these problems with logic restructuring poses new challenges, as the overall problem is more complex as compared to CMOS and algorithms and tools cannot be just adapted. This presentation will cover recent advancement in design automation for superconducting electronic circuits as well as address future developments in the field.