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IEEE Transactions on Applied Superconductivity

Rapid single-flux-quantum dual-rail logic for asynchronous circuits

Masaaki Maezawa, I. Kurosawa, Masahiro Aoyagi, Hiroshi Nakagawa, Y. Kameda, Takashi Nanya

Published Jun 1, 1997• 31 citations
Publisher

Abstract

Dual-rail logic circuit elements based on rapid single-flux-quantum (RSFQ) technology have been designed and simulated. The proposed circuits can operate asynchronously, since dual-rail data include timing information in themselves. Therefore dual-rail logic scheme has a possibility of solving some problems of RSFQ circuits with flow clocking, which would become more serious as operating speed and complexity of the circuit increase. Implementation of RSFQ dual-rail AND and XOR cells is described. A scheme of transfer-ring data from a flow-clocked circuit to a parallel dual-rail circuit is also proposed, which a fully asynchronous dual-rail demultiplexer.

DOI
10.1109/77.621796

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SAIEE Africa Research Journal•Sep 1, 2006•0 citations
Dual-rail logic circuit elements based on rapid single-flux-quantum (RSFQ) technology have been designed and simulated. The proposed circuits can operate asynchronously, since dual-rail data include timing information in themselves. Therefore dual-rail logic scheme has a possibility of solving some problems of RSFQ circuits with flow clocking, which would become more serious as operating speed and complexity of the circuit increase. Implementation of RSFQ dual-rail AND and XOR cells is described. A scheme of transfer-ring data from a flow-clocked circuit to a parallel dual-rail circuit is also proposed, which a fully asynchronous dual-rail demultiplexer.
We present a novel asynchronous RSFQ demultiplexer based on dual-rail information coding. The electrical scheme of the circuit is designed and optimized to maximize the margins of its elements and to improve the fabrication yield. This optimized scheme has been fabricated with the 4 µm 1 kA cm−2 Nb/Al2O3–Al/Nb technology of PTB-Braunschweig. The demultiplexer has been tested with different samples of the low-speed incoming data stream and in all cases a correct circuit functionality has been observed.
Superconductive Rapid Single Flux Quantum (RSFQ) logic and memory, in which ones and zeros are represented by the presence or absence within a timing window of quantized picosecond voltage pulse (/spl int/v(t)dt=h/2e=2.07 mV/spl middot/ps), corresponding to one SFQ, can be integrated into a digital computing system with an operating rate of several tens of GHz, based on the present Nb Josephson junction integrated circuit technology. It is the most promising technology beyond semiconductor transistors for low-power high-end computation. However, as the operating speed of circuits and systems increase, timing uncertainty from fabrication process variations makes global synchronization very hard. In this paper, we present a globally asynchronous, locally synchronous timing methodology for RSFQ digital design, which can solve the global synchronization problem. We also demonstrate the recent experimental results of some asynchronous circuits and systems implemented in RSFQ technology. Several key components such as a self-timed shift register, a self-timed demultiplexor, a Muller-C element, a completion detector, and a clock generator have been designed and tested. High speed operation has been confirmed up to 20 Gb/s for a prototype data buffer system, which consists two self-timed shift registers and an on-chip 5-38 GHz clock generator.
Rapid single flux quantum (RSFQ) logic is a digital circuit technology that in recent years has presented itself as an alternative to semiconductors in the application of ultra high speed, very low power applications. The optimal timing of digital circuits operating at hundreds of GHz is still a complex problem for both RSFQ and semiconductor technologies. The fact that most RSFQ gates require a clock signal to function makes this even more complex. Various RSFQ timing schemes have been adapted from semiconductor design methodologies, and some have been designed specifically for RSFQ. Currently, synchronous clocking schemes outperform other schemes, but with the scale of RSFQ circuits ever increasing, the proper use of timing schemes are becoming more crucial. This paper describes a new asynchronous self-timing scheme where the details of clock distribution and clocking are built into the logic gates. Tests were done on the newly developed asynchronous logic gates and an asynchronous full adder was implemented and tested
Superconducting logic gates need synchronization clock in order to synchronize the inputs for performing the Boolean functions properly; i.e. the inputs should arrive to the gate and the output is valid when the clock is in the high state. However, for large scale circuits, large clock routes impose limits on circuit design, such as clock skew, narrow timing tolerances, synchronization violation and system integrity. Dual-rail topology for asynchronous logic circuit design overcomes these limits to a satisfactory level, by eliminating the clocking routes and producing local clock pulses. In this manuscript, design of the dual-rail asynchronous logic gates (AND, OR and XOR) based on the superconducting quantum phase slip (QPS) is represented. As the dual-rail topology adds extra elements to the final circuit, in order to reduce the total number of elements, first, the timed QPS AND, OR and XOR gates, splitter, confluence buffer and coincidence junction with reduced number of elements are designed. Then these elements are used to design the corresponding final dual-rail asynchronous QPS gates. Proper operation of the proposed asynchronous gates are investigated by simulation results. Finally, delay analysis is provided in order to estimate operation frequency limit of the proposed asynchronous gates.
Rapid Single Flux Quantum (RSFQ) logic is a digital circuit technology that in recent years has presented itself as an alternative to semiconductors in the application of ultra high speed, very low power applications. The optimal timing of digital circuits operating at hundreds of Gigahertz is still a complex problem for both RSFQ and semiconductor technologies. The fact that most RSFQ gates require a clock signal to function makes this even more complex. Various RSFQ liming schemes have been adapted from semiconductor design methodologies, and some have been designed specifically for RSFQ. Currently, synchronous clocking schemes outperform other schemes, but with the scale of RSFQ circuits ever increasing, the proper use of timing schemes are becoming more crucial. This paper describes a new asynchronous self-timing scheme where the details of clock distribution and clocking are built into the logic gates. Tests were done on the newly developed asynchronous logic-gales and a asynchronous full adder was implemented and tested.