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Superconductor Science and Technology

An asynchronous rapid single-flux-quantum demultiplexer based on dual-rail information coding

Boyko Dimov, M. Khabipov, D Balashov, C.M. Brandt, F-Im Buchholz, J. Niemeyer, Friedrich Uhlmann

Published Apr 5, 2005• 1 citation
Publisher

Abstract

We present a novel asynchronous RSFQ demultiplexer based on dual-rail information coding. The electrical scheme of the circuit is designed and optimized to maximize the margins of its elements and to improve the fabrication yield. This optimized scheme has been fabricated with the 4 µm 1 kA cm−2 Nb/Al2O3–Al/Nb technology of PTB-Braunschweig. The demultiplexer has been tested with different samples of the low-speed incoming data stream and in all cases a correct circuit functionality has been observed.

DOI
10.1088/0953-2048/18/5/011

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We present a novel asynchronous RSFQ demultiplexer based on dual-rail information coding. The electrical scheme of the circuit is designed and optimized to maximize the margins of its elements and to improve the fabrication yield. This optimized scheme has been fabricated with the 4 µm 1 kA cm−2 Nb/Al2O3–Al/Nb technology of PTB-Braunschweig. The demultiplexer has been tested with different samples of the low-speed incoming data stream and in all cases a correct circuit functionality has been observed.
Dual-rail logic circuit elements based on rapid single-flux-quantum (RSFQ) technology have been designed and simulated. The proposed circuits can operate asynchronously, since dual-rail data include timing information in themselves. Therefore dual-rail logic scheme has a possibility of solving some problems of RSFQ circuits with flow clocking, which would become more serious as operating speed and complexity of the circuit increase. Implementation of RSFQ dual-rail AND and XOR cells is described. A scheme of transfer-ring data from a flow-clocked circuit to a parallel dual-rail circuit is also proposed, which a fully asynchronous dual-rail demultiplexer.
A demultiplexer (DMUX) is a key subsystem of rapid single flux quantum (RSFQ) circuits and systems in practical applications. High-speed data from RSFQ circuits should be converted into sufficiently low-speed ones for transmission to and processing by room temperature electronics. We designed, fabricated and successfully tested an RSFQ DMUX based on the synchronous shift-and-dump architecture whose advantages are modularity and compactness. A 1-to-8 DMUX was implemented using our standard cell library on 1.6 kA cm −2 Nb trilayer technology. Fully functional operation was confirmed by low speed testing. Experimental bias margins were as large as ±16%. Results of average voltage measurements implied that the DMUX was operated at data rates up to 25 Gb s −1 .
High-speed data acquisition and communication systems require fast multiplexing and demultiplexing of data. We are developing novel multiplexer/demultiplexer circuits using a dual-rail approach. A single cell of the demultiplexer is a toggle type B flip-flop. The demultiplexer operates at 95 GHz and its performance does not depend on the demultiplexing ratio. The dual-rail technique avoids racing between data and clock signals. The multiplexer circuit is based on RS type B flip-flops and works up to 60 GHz. The circuits are implemented in HYPRES' standard Nb process with a critical current density of 1.0 KA/cm/sup 2/.
We have developed a data-driven self-timed (DDST) rapid-single-flux-quantum (RSFQ) demultiplexer (demux) for the interface between on-chip high-speed RSFQ circuits and off-chip low-speed circuits. In order to eliminate the timing issue in a synchronous clocking system we employed the DDST architecture, where a clock signal is localized within a 2-bit basic demux module and dual rail lines are used to transfer the timing information between the modules. A larger demux can be produced simply by connecting the 2-bit modules in a tree structure. The DDST demux was designed for 10 Gb/s operation with sufficient dc bias margin using HYPRES 1 kA/cm/sup 2/ Nb process. We have successfully tested operation of the 2-bit demux up to 18 GHz using the DDST on-chip high-speed test system which was developed in our group.