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IEEE Transactions on Applied Superconductivity

High-speed asynchronous data multiplexing/demultiplexing

Alex F. Kirichenko

Published Jun 1, 1999• 10 citations
Publisher

Abstract

High-speed data acquisition and communication systems require fast multiplexing and demultiplexing of data. We are developing novel multiplexer/demultiplexer circuits using a dual-rail approach. A single cell of the demultiplexer is a toggle type B flip-flop. The demultiplexer operates at 95 GHz and its performance does not depend on the demultiplexing ratio. The dual-rail technique avoids racing between data and clock signals. The multiplexer circuit is based on RS type B flip-flops and works up to 60 GHz. The circuits are implemented in HYPRES' standard Nb process with a critical current density of 1.0 KA/cm/sup 2/.

DOI
10.1109/77.783915

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High-speed data acquisition and communication systems require fast multiplexing and demultiplexing of data. We are developing novel multiplexer/demultiplexer circuits using a dual-rail approach. A single cell of the demultiplexer is a toggle type B flip-flop. The demultiplexer operates at 95 GHz and its performance does not depend on the demultiplexing ratio. The dual-rail technique avoids racing between data and clock signals. The multiplexer circuit is based on RS type B flip-flops and works up to 60 GHz. The circuits are implemented in HYPRES' standard Nb process with a critical current density of 1.0 KA/cm/sup 2/.
An 1:8 RSFQ demultiplexer (DEMUX) and an 8:1 RSFQ multiplexer (MUX) were designed, simulated and optimized to operate at about 20 GHz. Both the inputs and outputs of the DEMUX are complementary dual-rail signals. The basic 2-bit DEMUX module is a self-clocked dual-rail T flip-flop. This DEMUX has a simpler structure than an earlier version of a data-driven-self-timed (DDST) DEMUX developed in our laboratory; however its simulated dc bias margin is (-20%, +20%), which is lower than the more complex device (-29%, +29%). The MUX takes lower data rate single-rail inputs and combines them sequentially into a single output. The complementary output is recovered from the output itself to facilitate interfacing to other dual-rail circuits on chip. The calculated dc bias margin is (-30 %, +28%). Circuit functionality is verified for the 2-bit MUX and the 2-bit DEMUX at low speed. An on-chip high-speed test system is designed to evaluate operation of the MUX and DEMUX at 20 GHz. The circuits are fabricated using a 1 kA/cm/sup 2/ niobium process at both UCB and HYPRES.
We present a novel asynchronous RSFQ demultiplexer based on dual-rail information coding. The electrical scheme of the circuit is designed and optimized to maximize the margins of its elements and to improve the fabrication yield. This optimized scheme has been fabricated with the 4 µm 1 kA cm−2 Nb/Al2O3–Al/Nb technology of PTB-Braunschweig. The demultiplexer has been tested with different samples of the low-speed incoming data stream and in all cases a correct circuit functionality has been observed.
We have experimentally demonstrated high-speed operation of RSFQ circuits using on-chip testing system and confirmed normal operation up to 30 GHz. The system includes high-frequency pulse generators and shift registers (SRs) serving as an interface circuit between high-speed internal signals and low-speed external signals. We adopted two ladder-type pulse generators. One generates clock pulses of 10 GHz and the other generates 25 GHz. By increasing bias currents of JTLs, clock pulses can be generated at higher frequency. By using the system, an SR and a T flip-flop (TFF) gate are examined. The circuits were fabricated by NEC's standard process based on Nb/AlO x /Nb junction technology with J c = 2.5 kA cm -2 . We optimized circuit parameters by using Monte Carlo simulation. In addition, the effect of parasitic inductances can be reduced by decreasing I c . As a result, the systems for SR and TFF worked correctly up to 30 GHz and 27.5 GHz, respectively. The SR and TFF have wide bias margins of ±39% and ±20%, respectively. We confirmed that the bias margins of the SR are independent of operation frequency. The limits of operation frequency are thought to be much higher than 30 GHz.
We have developed a data-driven self-timed (DDST) rapid-single-flux-quantum (RSFQ) demultiplexer (demux) for the interface between on-chip high-speed RSFQ circuits and off-chip low-speed circuits. In order to eliminate the timing issue in a synchronous clocking system we employed the DDST architecture, where a clock signal is localized within a 2-bit basic demux module and dual rail lines are used to transfer the timing information between the modules. A larger demux can be produced simply by connecting the 2-bit modules in a tree structure. The DDST demux was designed for 10 Gb/s operation with sufficient dc bias margin using HYPRES 1 kA/cm/sup 2/ Nb process. We have successfully tested operation of the 2-bit demux up to 18 GHz using the DDST on-chip high-speed test system which was developed in our group.
Dual-rail logic circuit elements based on rapid single-flux-quantum (RSFQ) technology have been designed and simulated. The proposed circuits can operate asynchronously, since dual-rail data include timing information in themselves. Therefore dual-rail logic scheme has a possibility of solving some problems of RSFQ circuits with flow clocking, which would become more serious as operating speed and complexity of the circuit increase. Implementation of RSFQ dual-rail AND and XOR cells is described. A scheme of transfer-ring data from a flow-clocked circuit to a parallel dual-rail circuit is also proposed, which a fully asynchronous dual-rail demultiplexer.
We have designed, fabricated, and successfully tested a Time-to-Digital converter (TDC). The TDC circuit consists of superconductive counters based on toggle flip-flops with destructive readout, shift registers, parallel-to-serial converters, and pulse detectors. The value of the counter is latched while the counter is operating at full speed. The TDC resolution is directly determined by the maximum counter speed, or 50 ps for an available 20 GHz clock rate. The circuits are implemented in HYPRES' standard Nb process with a critical current density of 1.0 kA/cm/sup 2/ using HYPRES' library of standard RSFQ cells.