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International Conference on Applied Superconductivity and Electromagnetic Devices

Novel dual-rail gates structure and their application in 1-bit-full-adder

Lei Wang, Boran Guan

Published Sep 1, 2009• 0 citations
Publisher

Abstract

Superconductive rapid single flux quantum (RSFQ) digital computing system has the tendency to achieve the operating rate of several hundred GHz. Compare to the semiconductor partner, with the pulse width about picoseconds and clock rate of several hundred GHz, the timing uncertainty from fabrication process variations makes it impossible to achieve the large scale integrated chip with global synchronization architecture. Many efforts, in this field, have been made to construct the asynchronous RSFQ timing conformation with advanced performances. In this paper, a novel AND gate and a novel universal gate based on dual-rail methodology are proposed. The new gates have the advantages in less Josephson junction count and less signal time delay over the previous published version. A 1-bit-full-adder has been implemented based on the novel gates, the simulation shows that they function well and can be considered as the candidates in the system construction. Furthermore, the properties of the gates circuits have also been analyzed numerically with its sensitivity for parameters and tolerant for margin error.

DOI
10.1109/asemd.2009.5306623

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Superconductive rapid single flux quantum (RSFQ) digital computing system has the tendency to achieve the operating rate of several hundred GHz. Compare to the semiconductor partner, with the pulse width about picoseconds and clock rate of several hundred GHz, the timing uncertainty from fabrication process variations makes it impossible to achieve the large scale integrated chip with global synchronization architecture. Many efforts, in this field, have been made to construct the asynchronous RSFQ timing conformation with advanced performances. In this paper, a novel AND gate and a novel universal gate based on dual-rail methodology are proposed. The new gates have the advantages in less Josephson junction count and less signal time delay over the previous published version. A 1-bit-full-adder has been implemented based on the novel gates, the simulation shows that they function well and can be considered as the candidates in the system construction. Furthermore, the properties of the gates circuits have also been analyzed numerically with its sensitivity for parameters and tolerant for margin error.
Rapid single flux quantum (RSFQ) logic is a digital circuit technology that in recent years has presented itself as an alternative to semiconductors in the application of ultra high speed, very low power applications. The optimal timing of digital circuits operating at hundreds of GHz is still a complex problem for both RSFQ and semiconductor technologies. The fact that most RSFQ gates require a clock signal to function makes this even more complex. Various RSFQ timing schemes have been adapted from semiconductor design methodologies, and some have been designed specifically for RSFQ. Currently, synchronous clocking schemes outperform other schemes, but with the scale of RSFQ circuits ever increasing, the proper use of timing schemes are becoming more crucial. This paper describes a new asynchronous self-timing scheme where the details of clock distribution and clocking are built into the logic gates. Tests were done on the newly developed asynchronous logic gates and an asynchronous full adder was implemented and tested
Superconductive Rapid Single Flux Quantum (RSFQ) logic and memory, in which ones and zeros are represented by the presence or absence within a timing window of quantized picosecond voltage pulse (/spl int/v(t)dt=h/2e=2.07 mV/spl middot/ps), corresponding to one SFQ, can be integrated into a digital computing system with an operating rate of several tens of GHz, based on the present Nb Josephson junction integrated circuit technology. It is the most promising technology beyond semiconductor transistors for low-power high-end computation. However, as the operating speed of circuits and systems increase, timing uncertainty from fabrication process variations makes global synchronization very hard. In this paper, we present a globally asynchronous, locally synchronous timing methodology for RSFQ digital design, which can solve the global synchronization problem. We also demonstrate the recent experimental results of some asynchronous circuits and systems implemented in RSFQ technology. Several key components such as a self-timed shift register, a self-timed demultiplexor, a Muller-C element, a completion detector, and a clock generator have been designed and tested. High speed operation has been confirmed up to 20 Gb/s for a prototype data buffer system, which consists two self-timed shift registers and an on-chip 5-38 GHz clock generator.
Rapid Single Flux Quantum (RSFQ) logic is a digital circuit technology that in recent years has presented itself as an alternative to semiconductors in the application of ultra high speed, very low power applications. The optimal timing of digital circuits operating at hundreds of Gigahertz is still a complex problem for both RSFQ and semiconductor technologies. The fact that most RSFQ gates require a clock signal to function makes this even more complex. Various RSFQ liming schemes have been adapted from semiconductor design methodologies, and some have been designed specifically for RSFQ. Currently, synchronous clocking schemes outperform other schemes, but with the scale of RSFQ circuits ever increasing, the proper use of timing schemes are becoming more crucial. This paper describes a new asynchronous self-timing scheme where the details of clock distribution and clocking are built into the logic gates. Tests were done on the newly developed asynchronous logic-gales and a asynchronous full adder was implemented and tested.
At the typical operating temperature of 4.2 K, the theoretical upper limit of the clock frequency of the Low-Temperature Superconductive (LTS) Nb based Rapid Single Flux Quantum (RSFQ) digital circuits is several hundred GHz. Nevertheless, the few middle-scale RSFQ circuits reported on up to now operate at only some tens of GHz. An important performance-limiting factor is in this case the clock signal distribution, so nowadays asynchronous RSFQ designs are often considered. Our previous studies have shown that it is an important advantage of a given asynchronous RSFQ cell library to contain gates with tunable delays. We have already shown by simulations that the RSFQ gate delays are best adjusted by changing the Stewart-McCumber parameter /spl beta//sub c/ of the Josephson junctions-this method tunes the delay within a large interval of values while scarcely affecting the margins and the fabrication yield of the RSFQ gates. In order to prove this statement experimentally, we have designed, fabricated, and tested several ring-shaped oscillators with identical topologies but different Stewart-McCumber parameters of the Josephson junctions. Their operating speeds and margins are measured and compared.
We have developed a novel, so-called "push-forward" design approach in Rapid Single-Flux-Quantum (RSFQ) logic. This approach leads to a more efficient circuit design at the gate level using fewer Josephson junctions combined with reasonable circuit parameter margins. Other advantages include higher operational speed and smaller power dissipation. This novel method is based on a specific type of interaction (pushing forward) between single flux quanta already stored by RSFQ gates and newly arriving data SFQ pulses. It implies a reuse of an internal gate memory as well as realization of multi-quantum storage. Using this push-forward design approach, we have designed, optimized, fabricated, and successfully tested two versions of Carry-Save Serial Adders for digital signal processing applications.>