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Digest of technical papers/Digest of technical papers - IEEE International Solid-State Circuits Conference

Josephson-CMOS memories

Uttam Ghoshal, David F. Hebert, T. Van Duzer

Published Jan 1, 1993• 18 citations
Publisher

Abstract

Results of an experiment on Josephson-CMOS memories show that these circuits have the potential to remove the memory bottleneck faced by superconductive electronics and the speed limitations of purely CMOS memories. The experiment demonstrates monolithic integrated Nb-AlO/sub x/-Nb Josephson-CMOS digital circuits operating at 4 K, the feasibility of Josephson-CMOS interface circuits with conversion delays of less than 150 ps, and fluxoelectronic current sensing of MOS RAM and CAM (content-addressable memory) cells using 4JL gates and SQUIDs (superconducting quantum interference devices).>

DOI
10.1109/isscc.1993.280086

Related papers

Josephson-CMOS Hybrid Memories

Qingguo Liu, Qingguo Liu

Abstract : Lack of high-density, fast and memory has been a long-standing problem in superconducting digital electronics. Alternative Josephson-junction-based memory cells and peripheral circuits have intrinsic problems which impede the application of that kind of memory. The CMOS-Josephson hybrid memory idea was proposed in 1992 to circumvent this problem. In the present work we have designed and demonstrated a 64-kb CMOS-Josephson hybrid memory working at 1 GHz. In order to make the hybrid idea practical, a complete and comprehensive 4 K short-channel CMOS model for digital circuits was developed for this dissertation. It has been used in the design of the memory core and peripheral circuits. A fast hybrid interface circuit that transforms single-flux-quantum millivolt 2-ps pulse signals to CMOS volt-level signals has been studied and the optimized design has been completed. Using a nonvolatile cryogenic 3-T DRAM cell, the memory core is designed in such a way that the access time is much less than for room-temperature operation, not only because of the performance upgrade due to the temperature decrease but also because of a different reading mechanism. Fabricated by commercial submicron CMOS processes (0.25 microns and 0.18 microns) and a Nb/AlOx/Nb Josephson-junction process with 2.5 kA/cm2 tunneling current density, the memory chips were bonded together by direct wire-bonding and by flip-chip bump-bonding and tested at low frequencies, high frequencies, respectively. A subnanosecond access time is obtained both from simulations and experiments. The power for an interface circuit is measured to be 0.6 mW. The memory core consumes even less power. The total power consumption depends on the operation mode of the memory and is calculated to be 10 mW for reading and 28 mW for writing. Simulations also indicate that, with more advanced semiconductor and superconductor technologies, larger and faster hybrid memories are expected to be achievable in the future.

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A 4K Josephson memory

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The authors describe the design and experimental performance of a 4 K*1-bit Josephson (RAM). For high-speed memory operation, the authors have developed a compact AND gate for the decoder, a high-voltage driver gate, and a capacitively coupled single-flux quantum memory cell. The 4 K memory was designed using these gates and cell and was fabricated with Nb/AlO/sub x//Nb junctions. The minimum access time was 590 ps, and the total power dissipation was 19 mW.>

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For broadband data communication between Josephson and CMOS digital systems, amplification of small Josephson-output signals and synchronization between the systems are important issues. We present an interface circuit for a Josephson-CMOS hybrid digital system. The interface circuit consists of a parallel-in-parallel-out (PIPO) circuit and built-in Josephson-MOS amplifiers. The PIPO circuit, implemented based on 4JL latching logic technology, performs synchronized data transfer between the Josephson and CMOS circuits. The Josephson-MOS amplifiers consists of stacked Josephson junctions (Suzuki stacks) and MOS inverters which are monolithically integrated on a chip. The circuits have been designed, fabricated and tested. We have successfully confirmed correct operation of the circuits.

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AC-and DC-powered subnanosecond 1-kbit Josephson cache memory design

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The address decoders, address line drivers, and sense circuits of the fully decoded memory consist of resistor-coupled Josephson logic circuits to realize fast access. The memory cell is constructed from two three-junction symmetric SQUID (superconducting quantum interface device) gates, and a four-flux-quanta storage loop for enabling bipolar current drive. This memory configuration has intrinsic advantages in regard to magnetic flux trapping in address lines and a gate circuit latch-up problem over a DC-powered memory constructed from inductor coupled gates. Individual control and cell circuits were fabricated, using a lead-alloy process, and their operation was verified. A 570-ps read access time is estimated as the sum measured 280-ps decoding time, and calculated 130-ps address line current rising time, 110-ps sense time, and 50-ps signal propagation time. The 1-kb chip is designed to consume 9 mW without voltage regulators.>

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64-kb Hybrid Josephson-CMOS 4 Kelvin RAM With 400 ps Access Time and 12 mW Read Power

T. Van Duzer, Lizhen Zheng, Stephen R. Whiteley +4 more

We have designed, simulated, fabricated, and tested a 64-kb hybrid Josephson-CMOS memory using a 5 mm × 5 mm Josephson interface chip and a 2.0 × 1.5 mm CMOS chip. The Josephson chip uses the Hypres 4.5 kA/cm2niobium technology and the CMOS chip is made using the TSMC 65-nm technology. The chips are connected using short wire bonds in a piggy-back package. The chip sizes and pad layouts have been constrained to allow testing in our wideband American Cryoprobe Model BCP-2 test probe to measure ultrashort delays. The test signals of 5-mV amplitude are chosen to represent the signals that would be supplied to the memory in a digital computing or signal processing system. Each input signal is first amplified in a four-junction logic gate driving a Suzuki stack, which, in turn, drives a highly sensitive CMOS comparator that raises the signal to volt level. Such amplifiers are provided for the address, data, read, and write inputs to the CMOS memory. Output currents from the memory cells are detected by ultrafast four-junction logic gates providing 5-mV output signals; an equivalent arrangement was used for the delay tests. The overall read delay is the access time, which we find to be about 400 ps. We extrapolate from the measured and calculated power dissipation in this partially accessed 64-kb memory to a fully accessed 64-kb memory and find the expected overall read power dissipation to be about 12 mW for operation at 1 GHz.

IEEE Transactions on Applied Superconductivity•Nov 28, 2012•90 citations

Potential of superconductive josephson tunneling technology for ultrahigh performance memories and processors

W. Anacker

The potential of a new technology, based on the superconducting Josephson tunneling effect, has been assessed for use in high-speed computer systems. Josephson tunneling circuits for memory and logic functions can be switched at sub-nanosecond delay, do not require standby power, and dissipate extremely low energy, typically less than 10-13joule during fast switching operation. High-speed circuits with high packing densities, not limited by power dissipation problems, can therefore be expected. Low thermal noise at cryogenic temperatures ensures reliable operation despite the low energy switching signal. Practically lossless signal transmission via superconducting lines can be exploited for high-speed operation even when sizeable memory and logic modules are assembled. Two random access memory modules have been designed on the basis of single device experiments. Operational characteristics leading to the conclusion that 30 Mbit capacity, less than 1 watt refrigeration requirement (at 3.6° K) and cycle times of 40 ns (in one case) and 15 ns (in the second case), can be achieved are presented.

IEEE Transactions on Magnetics•Dec 1, 1969•72 citations
Results of an experiment on Josephson-CMOS memories show that these circuits have the potential to remove the memory bottleneck faced by superconductive electronics and the speed limitations of purely CMOS memories. The experiment demonstrates monolithic integrated Nb-AlO/sub x/-Nb Josephson-CMOS digital circuits operating at 4 K, the feasibility of Josephson-CMOS interface circuits with conversion delays of less than 150 ps, and fluxoelectronic current sensing of MOS RAM and CAM (content-addressable memory) cells using 4JL gates and SQUIDs (superconducting quantum interference devices).>
Abstract : Lack of high-density, fast and memory has been a long-standing problem in superconducting digital electronics. Alternative Josephson-junction-based memory cells and peripheral circuits have intrinsic problems which impede the application of that kind of memory. The CMOS-Josephson hybrid memory idea was proposed in 1992 to circumvent this problem. In the present work we have designed and demonstrated a 64-kb CMOS-Josephson hybrid memory working at 1 GHz. In order to make the hybrid idea practical, a complete and comprehensive 4 K short-channel CMOS model for digital circuits was developed for this dissertation. It has been used in the design of the memory core and peripheral circuits. A fast hybrid interface circuit that transforms single-flux-quantum millivolt 2-ps pulse signals to CMOS volt-level signals has been studied and the optimized design has been completed. Using a nonvolatile cryogenic 3-T DRAM cell, the memory core is designed in such a way that the access time is much less than for room-temperature operation, not only because of the performance upgrade due to the temperature decrease but also because of a different reading mechanism. Fabricated by commercial submicron CMOS processes (0.25 microns and 0.18 microns) and a Nb/AlOx/Nb Josephson-junction process with 2.5 kA/cm2 tunneling current density, the memory chips were bonded together by direct wire-bonding and by flip-chip bump-bonding and tested at low frequencies, high frequencies, respectively. A subnanosecond access time is obtained both from simulations and experiments. The power for an interface circuit is measured to be 0.6 mW. The memory core consumes even less power. The total power consumption depends on the operation mode of the memory and is calculated to be 10 mW for reading and 28 mW for writing. Simulations also indicate that, with more advanced semiconductor and superconductor technologies, larger and faster hybrid memories are expected to be achievable in the future.
For broadband data communication between Josephson and CMOS digital systems, amplification of small Josephson-output signals and synchronization between the systems are important issues. We present an interface circuit for a Josephson-CMOS hybrid digital system. The interface circuit consists of a parallel-in-parallel-out (PIPO) circuit and built-in Josephson-MOS amplifiers. The PIPO circuit, implemented based on 4JL latching logic technology, performs synchronized data transfer between the Josephson and CMOS circuits. The Josephson-MOS amplifiers consists of stacked Josephson junctions (Suzuki stacks) and MOS inverters which are monolithically integrated on a chip. The circuits have been designed, fabricated and tested. We have successfully confirmed correct operation of the circuits.
The address decoders, address line drivers, and sense circuits of the fully decoded memory consist of resistor-coupled Josephson logic circuits to realize fast access. The memory cell is constructed from two three-junction symmetric SQUID (superconducting quantum interface device) gates, and a four-flux-quanta storage loop for enabling bipolar current drive. This memory configuration has intrinsic advantages in regard to magnetic flux trapping in address lines and a gate circuit latch-up problem over a DC-powered memory constructed from inductor coupled gates. Individual control and cell circuits were fabricated, using a lead-alloy process, and their operation was verified. A 570-ps read access time is estimated as the sum measured 280-ps decoding time, and calculated 130-ps address line current rising time, 110-ps sense time, and 50-ps signal propagation time. The 1-kb chip is designed to consume 9 mW without voltage regulators.>
We have designed, simulated, fabricated, and tested a 64-kb hybrid Josephson-CMOS memory using a 5 mm × 5 mm Josephson interface chip and a 2.0 × 1.5 mm CMOS chip. The Josephson chip uses the Hypres 4.5 kA/cm2niobium technology and the CMOS chip is made using the TSMC 65-nm technology. The chips are connected using short wire bonds in a piggy-back package. The chip sizes and pad layouts have been constrained to allow testing in our wideband American Cryoprobe Model BCP-2 test probe to measure ultrashort delays. The test signals of 5-mV amplitude are chosen to represent the signals that would be supplied to the memory in a digital computing or signal processing system. Each input signal is first amplified in a four-junction logic gate driving a Suzuki stack, which, in turn, drives a highly sensitive CMOS comparator that raises the signal to volt level. Such amplifiers are provided for the address, data, read, and write inputs to the CMOS memory. Output currents from the memory cells are detected by ultrafast four-junction logic gates providing 5-mV output signals; an equivalent arrangement was used for the delay tests. The overall read delay is the access time, which we find to be about 400 ps. We extrapolate from the measured and calculated power dissipation in this partially accessed 64-kb memory to a fully accessed 64-kb memory and find the expected overall read power dissipation to be about 12 mW for operation at 1 GHz.
The potential of a new technology, based on the superconducting Josephson tunneling effect, has been assessed for use in high-speed computer systems. Josephson tunneling circuits for memory and logic functions can be switched at sub-nanosecond delay, do not require standby power, and dissipate extremely low energy, typically less than 10-13joule during fast switching operation. High-speed circuits with high packing densities, not limited by power dissipation problems, can therefore be expected. Low thermal noise at cryogenic temperatures ensures reliable operation despite the low energy switching signal. Practically lossless signal transmission via superconducting lines can be exploited for high-speed operation even when sizeable memory and logic modules are assembled. Two random access memory modules have been designed on the basis of single device experiments. Operational characteristics leading to the conclusion that 30 Mbit capacity, less than 1 watt refrigeration requirement (at 3.6° K) and cycle times of 40 ns (in one case) and 15 ns (in the second case), can be achieved are presented.