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IEEE Transactions on Applied Superconductivity

64-kb Hybrid Josephson-CMOS 4 Kelvin RAM With 400 ps Access Time and 12 mW Read Power

T. Van Duzer, Lizhen Zheng, Stephen R. Whiteley, Hoki Kim, Jae-Woo Kim, Xiaofan Meng, Thomas Ortlepp

Published Nov 28, 2012• 90 citations

Abstract

We have designed, simulated, fabricated, and tested a 64-kb hybrid Josephson-CMOS memory using a 5 mm × 5 mm Josephson interface chip and a 2.0 × 1.5 mm CMOS chip. The Josephson chip uses the Hypres 4.5 kA/cm2niobium technology and the CMOS chip is made using the TSMC 65-nm technology. The chips are connected using short wire bonds in a piggy-back package. The chip sizes and pad layouts have been constrained to allow testing in our wideband American Cryoprobe Model BCP-2 test probe to measure ultrashort delays. The test signals of 5-mV amplitude are chosen to represent the signals that would be supplied to the memory in a digital computing or signal processing system. Each input signal is first amplified in a four-junction logic gate driving a Suzuki stack, which, in turn, drives a highly sensitive CMOS comparator that raises the signal to volt level. Such amplifiers are provided for the address, data, read, and write inputs to the CMOS memory. Output currents from the memory cells are detected by ultrafast four-junction logic gates providing 5-mV output signals; an equivalent arrangement was used for the delay tests. The overall read delay is the access time, which we find to be about 400 ps. We extrapolate from the measured and calculated power dissipation in this partially accessed 64-kb memory to a fully accessed 64-kb memory and find the expected overall read power dissipation to be about 12 mW for operation at 1 GHz.

DOI: 10.1109/tasc.2012.2230294

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We present hybridization of Josephson, CMOS, and nanocryotron (nTron) devices for a large-scale cryogenic memory application. The memory system proposed here is dynamic random access memory composed of address decoders based on an energy-efficient rapid single-flux-quantum logic, nTron line drivers, a CMOS memory cell array, and Josephson current sensors. Because drivers with voltage amplification and decoders are the major causes of power dissipation in the conventional Josephson-CMOS hybrid memory, drastic reduction in power consumption is expected. We show estimates that the power consumption of a 16-Mb memory is reduced to 1.36-2.77 mW, approximately 1/12 of the conventional Josephson-CMOS hybrid memory, and the access time is 0.78 ns for a read operation, when we assume a 65-nm CMOS process and a 1.0-μm Nb/AlOx/Nb process. In the preliminary experiment, we fabricated nTrons using NbTiN thin film that are suitable for hybrid memory implementation, and measured with eight-transistor static random access memory cells fabricated using the Rohm 0.18-μm CMOS process. We successfully triggered the nTron into the normal state, and observed output voltage of ~0.1 V at 13.5 K. The experimental results support the potential of the hybrid memory using NbTiN nTrons.

We have been developing a Josephson/CMOS hybrid memory, which enables sub-nanosecond access time, in order to overcome a memory bottleneck in single-flux-quantum (SFQ) digital systems. In our previous study, we obtained the access time of about 1.2ns in a 16-kb hybrid memory system using a 0.35µm CMOS process, but observed unexpected double peaks in histograms of access-time measurements. In this study, we designed a 64-kb hybrid memory system using a 0.18µm CMOS process. We considered that the double peak effect is due to parasitic capacitances at the bonding pad of Josephson and CMOS chips and reduced them in the new design. Measured access time is about 1.4ns, which agrees well with simulation results. The double peaks in the histogram were completely removed in the new results.