Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Log inSign up
Challenges
Datasets
Workspaces
Papers
Discussions
Leaderboard
Blog
Job Board
Q3AS

© 2026 Aqora Quantum S.A.S.

TermsPrivacyLegal Notice

IEICE Electronics Express

Access time measurement of 64-kb Josephson-CMOS hybrid memories using SFQ time-to-digital converter

Yuji Okamoto, Hyunjoo Jin, Yaguchi Kenta, Yuki Yamanashi, Nobuyuki Yoshikawa

Published Jan 1, 2010• 1 citation
Publisher

Abstract

We have been developing a Josephson/CMOS hybrid memory, which enables sub-nanosecond access time, in order to overcome a memory bottleneck in single-flux-quantum (SFQ) digital systems. In our previous study, we obtained the access time of about 1.2ns in a 16-kb hybrid memory system using a 0.35µm CMOS process, but observed unexpected double peaks in histograms of access-time measurements. In this study, we designed a 64-kb hybrid memory system using a 0.18µm CMOS process. We considered that the double peak effect is due to parasitic capacitances at the bonding pad of Josephson and CMOS chips and reduced them in the new design. Measured access time is about 1.4ns, which agrees well with simulation results. The double peaks in the histogram were completely removed in the new results.

DOI
10.1587/elex.7.320

Related papers

Access time measurements of Josephson–CMOS hybrid memory using single-flux-quantum circuits

Nobuyuki Yoshikawa, M Tokuda, T. Tomida +4 more

We have measured the access time of a 16-kbit Josephson–CMOS hybrid memory by using a single-flux-quantum (SFQ) delay measurement system. The delay measurement system is composed of a Josephson latching driver for generating input signals for the memory, an SFQ clock generator and counter for measuring the time interval, and a current-sense circuit for detecting the current output from the memory. The time resolution of the system corresponds to a clock period of the clock generator, which is 50 ps in our design. In these preliminary measurements, we have observed a memory access time of about 4 ns, where the parasitic capacitance of the bonding pad of the Josephson chip limits the access time at present. This is the first demonstration of the access time measurement of a complete Josephson–CMOS hybrid memory.

Superconductor Science and Technology•Mar 16, 2006•17 citations

64-kb Hybrid Josephson-CMOS 4 Kelvin RAM With 400 ps Access Time and 12 mW Read Power

T. Van Duzer, Lizhen Zheng, Stephen R. Whiteley +4 more

We have designed, simulated, fabricated, and tested a 64-kb hybrid Josephson-CMOS memory using a 5 mm × 5 mm Josephson interface chip and a 2.0 × 1.5 mm CMOS chip. The Josephson chip uses the Hypres 4.5 kA/cm2niobium technology and the CMOS chip is made using the TSMC 65-nm technology. The chips are connected using short wire bonds in a piggy-back package. The chip sizes and pad layouts have been constrained to allow testing in our wideband American Cryoprobe Model BCP-2 test probe to measure ultrashort delays. The test signals of 5-mV amplitude are chosen to represent the signals that would be supplied to the memory in a digital computing or signal processing system. Each input signal is first amplified in a four-junction logic gate driving a Suzuki stack, which, in turn, drives a highly sensitive CMOS comparator that raises the signal to volt level. Such amplifiers are provided for the address, data, read, and write inputs to the CMOS memory. Output currents from the memory cells are detected by ultrafast four-junction logic gates providing 5-mV output signals; an equivalent arrangement was used for the delay tests. The overall read delay is the access time, which we find to be about 400 ps. We extrapolate from the measured and calculated power dissipation in this partially accessed 64-kb memory to a fully accessed 64-kb memory and find the expected overall read power dissipation to be about 12 mW for operation at 1 GHz.

IEEE Transactions on Applied Superconductivity•Nov 28, 2012•90 citations

Josephson-CMOS Hybrid Memories

Qingguo Liu, Qingguo Liu

Abstract : Lack of high-density, fast and memory has been a long-standing problem in superconducting digital electronics. Alternative Josephson-junction-based memory cells and peripheral circuits have intrinsic problems which impede the application of that kind of memory. The CMOS-Josephson hybrid memory idea was proposed in 1992 to circumvent this problem. In the present work we have designed and demonstrated a 64-kb CMOS-Josephson hybrid memory working at 1 GHz. In order to make the hybrid idea practical, a complete and comprehensive 4 K short-channel CMOS model for digital circuits was developed for this dissertation. It has been used in the design of the memory core and peripheral circuits. A fast hybrid interface circuit that transforms single-flux-quantum millivolt 2-ps pulse signals to CMOS volt-level signals has been studied and the optimized design has been completed. Using a nonvolatile cryogenic 3-T DRAM cell, the memory core is designed in such a way that the access time is much less than for room-temperature operation, not only because of the performance upgrade due to the temperature decrease but also because of a different reading mechanism. Fabricated by commercial submicron CMOS processes (0.25 microns and 0.18 microns) and a Nb/AlOx/Nb Josephson-junction process with 2.5 kA/cm2 tunneling current density, the memory chips were bonded together by direct wire-bonding and by flip-chip bump-bonding and tested at low frequencies, high frequencies, respectively. A subnanosecond access time is obtained both from simulations and experiments. The power for an interface circuit is measured to be 0.6 mW. The memory core consumes even less power. The total power consumption depends on the operation mode of the memory and is calculated to be 10 mW for reading and 28 mW for writing. Simulations also indicate that, with more advanced semiconductor and superconductor technologies, larger and faster hybrid memories are expected to be achievable in the future.

•Nov 7, 2013•4 citations

Access Time Measurement of 64 kb Josephson/CMOS Hybrid Memories using SFQ Time-to-Digital Converter

Okamoto Yuji, Park Heejoung, Hyunjoo Jin +3 more

IEICE Technical Report; IEICE Tech. Rep.•Jan 18, 2008•0 citations

Demonstration of a Single-Flux-Quantum Microprocessor Operating With Josephson-CMOS Hybrid Memory

Yuki Hironaka, Yuki Yamanashi, Nobuyuki Yoshikawa

We have been developing Josephson-CMOS hybrid memory to realize large-scale single-flux-quantum (SFQ) digital systems. In this article, we present the first demonstration of a Josephson-cryo complementary-metal-oxide-semicoductor (CMOS) memory hybrid system composed of an SFQ microprocessor and cryo-CMOS memory. We designed a single-instruction SFQ microprocessor whose data memory is implemented using Josephson-CMOS hybrid memory with a 16 × 4-b accessible address space. The Josephson and CMOS circuits were fabricated using the AIST Nb standard process and the Rohm 180-nm process, respectively. Low-frequency tests confirmed the correct operation of the single instruction SUBNEG (subtract and branch if negative), which verifies the read and write operations of data between the SFQ microprocessor and the hybrid memory. We also demonstrate the operation of an integer sorting program, which is composed of 16 SUBNEG instructions.

IEEE Transactions on Applied Superconductivity•May 12, 2020•33 citations

Experimental Demonstration of 1.2-Gb/s/Channel Readout Operation of Josephson–CMOS Hybrid Memory

Yuki Hironaka, Nobuyuki Yoshikawa

In this study, we aimed to achieve high-speed readout operations of Josephson–CMOS hybrid memory. We first experimentally evaluated the timing margin in the readout operations of the hybrid memory. In single-channel bit line measurements, we confirmed that the hybrid memory could work at a 1-GHz memory clock frequency with a timing margin as high as 0.63 ns. Subsequently, we designed and measured a Josephson–CMOS hybrid accumulator circuit to demonstrate high-speed read operations of the hybrid memory. The core design of the Josephson–CMOS hybrid memory follows our previous design. We introduced a sequential-access read-only CMOS memory and a single-flux-quantum accumulator into a test circuit, enabling high-speed measurement of Josephson–CMOS hybrid memory with only two high-speed external inputs. We designed and fabricated a test circuit using the Rohm 180-nm CMOS process and the AIST-ADP2 Josephson process. In the measurement, we achieved correct operation of the test circuit, including the readout operation of the 32-b hybrid memory at a memory clock frequency as high as 1.2 GHz, corresponding to a 38.4-Gb/s readout.

IEEE Transactions on Applied Superconductivity•Oct 22, 2024•1 citation
We have been developing a Josephson/CMOS hybrid memory, which enables sub-nanosecond access time, in order to overcome a memory bottleneck in single-flux-quantum (SFQ) digital systems. In our previous study, we obtained the access time of about 1.2ns in a 16-kb hybrid memory system using a 0.35µm CMOS process, but observed unexpected double peaks in histograms of access-time measurements. In this study, we designed a 64-kb hybrid memory system using a 0.18µm CMOS process. We considered that the double peak effect is due to parasitic capacitances at the bonding pad of Josephson and CMOS chips and reduced them in the new design. Measured access time is about 1.4ns, which agrees well with simulation results. The double peaks in the histogram were completely removed in the new results.
We have measured the access time of a 16-kbit Josephson–CMOS hybrid memory by using a single-flux-quantum (SFQ) delay measurement system. The delay measurement system is composed of a Josephson latching driver for generating input signals for the memory, an SFQ clock generator and counter for measuring the time interval, and a current-sense circuit for detecting the current output from the memory. The time resolution of the system corresponds to a clock period of the clock generator, which is 50 ps in our design. In these preliminary measurements, we have observed a memory access time of about 4 ns, where the parasitic capacitance of the bonding pad of the Josephson chip limits the access time at present. This is the first demonstration of the access time measurement of a complete Josephson–CMOS hybrid memory.
We have designed, simulated, fabricated, and tested a 64-kb hybrid Josephson-CMOS memory using a 5 mm × 5 mm Josephson interface chip and a 2.0 × 1.5 mm CMOS chip. The Josephson chip uses the Hypres 4.5 kA/cm2niobium technology and the CMOS chip is made using the TSMC 65-nm technology. The chips are connected using short wire bonds in a piggy-back package. The chip sizes and pad layouts have been constrained to allow testing in our wideband American Cryoprobe Model BCP-2 test probe to measure ultrashort delays. The test signals of 5-mV amplitude are chosen to represent the signals that would be supplied to the memory in a digital computing or signal processing system. Each input signal is first amplified in a four-junction logic gate driving a Suzuki stack, which, in turn, drives a highly sensitive CMOS comparator that raises the signal to volt level. Such amplifiers are provided for the address, data, read, and write inputs to the CMOS memory. Output currents from the memory cells are detected by ultrafast four-junction logic gates providing 5-mV output signals; an equivalent arrangement was used for the delay tests. The overall read delay is the access time, which we find to be about 400 ps. We extrapolate from the measured and calculated power dissipation in this partially accessed 64-kb memory to a fully accessed 64-kb memory and find the expected overall read power dissipation to be about 12 mW for operation at 1 GHz.
Abstract : Lack of high-density, fast and memory has been a long-standing problem in superconducting digital electronics. Alternative Josephson-junction-based memory cells and peripheral circuits have intrinsic problems which impede the application of that kind of memory. The CMOS-Josephson hybrid memory idea was proposed in 1992 to circumvent this problem. In the present work we have designed and demonstrated a 64-kb CMOS-Josephson hybrid memory working at 1 GHz. In order to make the hybrid idea practical, a complete and comprehensive 4 K short-channel CMOS model for digital circuits was developed for this dissertation. It has been used in the design of the memory core and peripheral circuits. A fast hybrid interface circuit that transforms single-flux-quantum millivolt 2-ps pulse signals to CMOS volt-level signals has been studied and the optimized design has been completed. Using a nonvolatile cryogenic 3-T DRAM cell, the memory core is designed in such a way that the access time is much less than for room-temperature operation, not only because of the performance upgrade due to the temperature decrease but also because of a different reading mechanism. Fabricated by commercial submicron CMOS processes (0.25 microns and 0.18 microns) and a Nb/AlOx/Nb Josephson-junction process with 2.5 kA/cm2 tunneling current density, the memory chips were bonded together by direct wire-bonding and by flip-chip bump-bonding and tested at low frequencies, high frequencies, respectively. A subnanosecond access time is obtained both from simulations and experiments. The power for an interface circuit is measured to be 0.6 mW. The memory core consumes even less power. The total power consumption depends on the operation mode of the memory and is calculated to be 10 mW for reading and 28 mW for writing. Simulations also indicate that, with more advanced semiconductor and superconductor technologies, larger and faster hybrid memories are expected to be achievable in the future.
We have been developing Josephson-CMOS hybrid memory to realize large-scale single-flux-quantum (SFQ) digital systems. In this article, we present the first demonstration of a Josephson-cryo complementary-metal-oxide-semicoductor (CMOS) memory hybrid system composed of an SFQ microprocessor and cryo-CMOS memory. We designed a single-instruction SFQ microprocessor whose data memory is implemented using Josephson-CMOS hybrid memory with a 16 × 4-b accessible address space. The Josephson and CMOS circuits were fabricated using the AIST Nb standard process and the Rohm 180-nm process, respectively. Low-frequency tests confirmed the correct operation of the single instruction SUBNEG (subtract and branch if negative), which verifies the read and write operations of data between the SFQ microprocessor and the hybrid memory. We also demonstrate the operation of an integer sorting program, which is composed of 16 SUBNEG instructions.
In this study, we aimed to achieve high-speed readout operations of Josephson–CMOS hybrid memory. We first experimentally evaluated the timing margin in the readout operations of the hybrid memory. In single-channel bit line measurements, we confirmed that the hybrid memory could work at a 1-GHz memory clock frequency with a timing margin as high as 0.63 ns. Subsequently, we designed and measured a Josephson–CMOS hybrid accumulator circuit to demonstrate high-speed read operations of the hybrid memory. The core design of the Josephson–CMOS hybrid memory follows our previous design. We introduced a sequential-access read-only CMOS memory and a single-flux-quantum accumulator into a test circuit, enabling high-speed measurement of Josephson–CMOS hybrid memory with only two high-speed external inputs. We designed and fabricated a test circuit using the Rohm 180-nm CMOS process and the AIST-ADP2 Josephson process. In the measurement, we achieved correct operation of the test circuit, including the readout operation of the 32-b hybrid memory at a memory clock frequency as high as 1.2 GHz, corresponding to a 38.4-Gb/s readout.