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IEEE Transactions on Applied Superconductivity

Demonstration of a Single-Flux-Quantum Microprocessor Operating With Josephson-CMOS Hybrid Memory

Yuki Hironaka, Yuki Yamanashi, Nobuyuki Yoshikawa

Published May 12, 2020• 33 citations
Publisher

Abstract

We have been developing Josephson-CMOS hybrid memory to realize large-scale single-flux-quantum (SFQ) digital systems. In this article, we present the first demonstration of a Josephson-cryo complementary-metal-oxide-semicoductor (CMOS) memory hybrid system composed of an SFQ microprocessor and cryo-CMOS memory. We designed a single-instruction SFQ microprocessor whose data memory is implemented using Josephson-CMOS hybrid memory with a 16 × 4-b accessible address space. The Josephson and CMOS circuits were fabricated using the AIST Nb standard process and the Rohm 180-nm process, respectively. Low-frequency tests confirmed the correct operation of the single instruction SUBNEG (subtract and branch if negative), which verifies the read and write operations of data between the SFQ microprocessor and the hybrid memory. We also demonstrate the operation of an integer sorting program, which is composed of 16 SUBNEG instructions.

DOI
10.1109/tasc.2020.2994208

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IEEE Transactions on Applied Superconductivity•Jul 18, 2022•5 citations
We have been developing Josephson-CMOS hybrid memory to realize large-scale single-flux-quantum (SFQ) digital systems. In this article, we present the first demonstration of a Josephson-cryo complementary-metal-oxide-semicoductor (CMOS) memory hybrid system composed of an SFQ microprocessor and cryo-CMOS memory. We designed a single-instruction SFQ microprocessor whose data memory is implemented using Josephson-CMOS hybrid memory with a 16 × 4-b accessible address space. The Josephson and CMOS circuits were fabricated using the AIST Nb standard process and the Rohm 180-nm process, respectively. Low-frequency tests confirmed the correct operation of the single instruction SUBNEG (subtract and branch if negative), which verifies the read and write operations of data between the SFQ microprocessor and the hybrid memory. We also demonstrate the operation of an integer sorting program, which is composed of 16 SUBNEG instructions.
Single flux quantum (SFQ) digital circuits have shown the potential for high speed/low power computation applications. Unfortunately, because of the low integration density and low driving capability of SFQ circuits, realizing large-scale memories by using only SFQ circuits is still a challenge. Josephson-CMOS hybrid memory, hybridizing high-speed, low power SFQ circuits, and high-density CMOS memories is already proposed as a solution to the large-scale memory problem in RSFQ digital systems. In this article, an SFQ-based memory controller which works up to 10 GHz clock frequencies is designed for Josephson-CMOS hybrid memory systems. The memory controller acts as a SFQ/CMOS interface between the SFQ circuit and SRAM module and generates the required waveforms for SRAM read and write operations. The circuit which has 4-b data and 2-b address lines is fabricated with AIST 2.5 kA/cm2STP2 process and operations of the circuits are verified. To demonstrate the scalability of the circuit, memory controller was scaled to 8-b data and 13-b address to control of the 64kb SRAM. Operations of the scaled memory controller are verified with analog simulations. Scaled circuit consumes 0.76 mW power in an area of 1.64 mm × 1.60 mm.
In this study, we aimed to achieve high-speed readout operations of Josephson–CMOS hybrid memory. We first experimentally evaluated the timing margin in the readout operations of the hybrid memory. In single-channel bit line measurements, we confirmed that the hybrid memory could work at a 1-GHz memory clock frequency with a timing margin as high as 0.63 ns. Subsequently, we designed and measured a Josephson–CMOS hybrid accumulator circuit to demonstrate high-speed read operations of the hybrid memory. The core design of the Josephson–CMOS hybrid memory follows our previous design. We introduced a sequential-access read-only CMOS memory and a single-flux-quantum accumulator into a test circuit, enabling high-speed measurement of Josephson–CMOS hybrid memory with only two high-speed external inputs. We designed and fabricated a test circuit using the Rohm 180-nm CMOS process and the AIST-ADP2 Josephson process. In the measurement, we achieved correct operation of the test circuit, including the readout operation of the 32-b hybrid memory at a memory clock frequency as high as 1.2 GHz, corresponding to a 38.4-Gb/s readout.
We present hybridization of Josephson, CMOS, and nanocryotron (nTron) devices for a large-scale cryogenic memory application. The memory system proposed here is dynamic random access memory composed of address decoders based on an energy-efficient rapid single-flux-quantum logic, nTron line drivers, a CMOS memory cell array, and Josephson current sensors. Because drivers with voltage amplification and decoders are the major causes of power dissipation in the conventional Josephson-CMOS hybrid memory, drastic reduction in power consumption is expected. We show estimates that the power consumption of a 16-Mb memory is reduced to 1.36-2.77 mW, approximately 1/12 of the conventional Josephson-CMOS hybrid memory, and the access time is 0.78 ns for a read operation, when we assume a 65-nm CMOS process and a 1.0-μm Nb/AlOx/Nb process. In the preliminary experiment, we fabricated nTrons using NbTiN thin film that are suitable for hybrid memory implementation, and measured with eight-transistor static random access memory cells fabricated using the Rohm 0.18-μm CMOS process. We successfully triggered the nTron into the normal state, and observed output voltage of ~0.1 V at 13.5 K. The experimental results support the potential of the hybrid memory using NbTiN nTrons.
Abstract : Lack of high-density, fast and memory has been a long-standing problem in superconducting digital electronics. Alternative Josephson-junction-based memory cells and peripheral circuits have intrinsic problems which impede the application of that kind of memory. The CMOS-Josephson hybrid memory idea was proposed in 1992 to circumvent this problem. In the present work we have designed and demonstrated a 64-kb CMOS-Josephson hybrid memory working at 1 GHz. In order to make the hybrid idea practical, a complete and comprehensive 4 K short-channel CMOS model for digital circuits was developed for this dissertation. It has been used in the design of the memory core and peripheral circuits. A fast hybrid interface circuit that transforms single-flux-quantum millivolt 2-ps pulse signals to CMOS volt-level signals has been studied and the optimized design has been completed. Using a nonvolatile cryogenic 3-T DRAM cell, the memory core is designed in such a way that the access time is much less than for room-temperature operation, not only because of the performance upgrade due to the temperature decrease but also because of a different reading mechanism. Fabricated by commercial submicron CMOS processes (0.25 microns and 0.18 microns) and a Nb/AlOx/Nb Josephson-junction process with 2.5 kA/cm2 tunneling current density, the memory chips were bonded together by direct wire-bonding and by flip-chip bump-bonding and tested at low frequencies, high frequencies, respectively. A subnanosecond access time is obtained both from simulations and experiments. The power for an interface circuit is measured to be 0.6 mW. The memory core consumes even less power. The total power consumption depends on the operation mode of the memory and is calculated to be 10 mW for reading and 28 mW for writing. Simulations also indicate that, with more advanced semiconductor and superconductor technologies, larger and faster hybrid memories are expected to be achievable in the future.
We have measured the access time of a 16-kbit Josephson–CMOS hybrid memory by using a single-flux-quantum (SFQ) delay measurement system. The delay measurement system is composed of a Josephson latching driver for generating input signals for the memory, an SFQ clock generator and counter for measuring the time interval, and a current-sense circuit for detecting the current output from the memory. The time resolution of the system corresponds to a clock period of the clock generator, which is 50 ps in our design. In these preliminary measurements, we have observed a memory access time of about 4 ns, where the parasitic capacitance of the bonding pad of the Josephson chip limits the access time at present. This is the first demonstration of the access time measurement of a complete Josephson–CMOS hybrid memory.
We propose a compact single-flux-quantum (SFQ) lookup table (LUT) that uses CMOS decoder circuits for reconfiguration to improve scalability. Reconfiguration by external control currents. Ann×n-bit LUT is composed of a two-dimensional array of memory cells and cryo-CMOS decoders. The memory cell at the target address is set to a logic “1” state when the correspondingx- andy-directional control currents are both applied from the CMOS decoders and is reset to logic “0” when a reset current is applied. Cryo-CMOS decoders are integrated with the SFQ LUT to reduce the number of control current lines (from 2n+1 to 2log2n+2) from the room-temperature electronics for LUT reconfiguration. For demonstration, we designed and fabricated a 64-b SFQ LUT integrated with CMOS decoders using the AIST 2.5-kA/cm2Nb standard process and the Rohm 180-nm CMOS process. Experimental results confirm the correct functionality of the SFQ LUT reconfigured by the CMOS decoders. All operating SFQ memory cells in the experiment showed almost the same control current margins. The proposed reconfiguration method is scalable in terms of the number of interconnections and control current margins for SFQ memory cells.