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IEEE Transactions on Applied Superconductivity

An interface circuit for a Josephson-CMOS hybrid digital system

Makoto Suzuki, Masaaki Maezawa, Hidetaka Takato, Hiroshi Nakagawa, Fuminori Hirayama, Shogo Kiryu, Masahiro Aoyagi, T. Sekigawa, Alexandre Shoji

Published Jun 1, 1999• 22 citations
Publisher

Abstract

For broadband data communication between Josephson and CMOS digital systems, amplification of small Josephson-output signals and synchronization between the systems are important issues. We present an interface circuit for a Josephson-CMOS hybrid digital system. The interface circuit consists of a parallel-in-parallel-out (PIPO) circuit and built-in Josephson-MOS amplifiers. The PIPO circuit, implemented based on 4JL latching logic technology, performs synchronized data transfer between the Josephson and CMOS circuits. The Josephson-MOS amplifiers consists of stacked Josephson junctions (Suzuki stacks) and MOS inverters which are monolithically integrated on a chip. The circuits have been designed, fabricated and tested. We have successfully confirmed correct operation of the circuits.

DOI
10.1109/77.783738

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For broadband data communication between Josephson and CMOS digital systems, amplification of small Josephson-output signals and synchronization between the systems are important issues. We present an interface circuit for a Josephson-CMOS hybrid digital system. The interface circuit consists of a parallel-in-parallel-out (PIPO) circuit and built-in Josephson-MOS amplifiers. The PIPO circuit, implemented based on 4JL latching logic technology, performs synchronized data transfer between the Josephson and CMOS circuits. The Josephson-MOS amplifiers consists of stacked Josephson junctions (Suzuki stacks) and MOS inverters which are monolithically integrated on a chip. The circuits have been designed, fabricated and tested. We have successfully confirmed correct operation of the circuits.
In this study, we designed, fabricated, and experimentally tested a Josephson latching driver (JLD), a superconductor-to-semiconductor interface circuit for use in Josephson-CMOS hybrid memory, utilizing a 10-kA/cm2Nb process. The JLD is composed of a voltage driver known as a Suzuki stack and a Josephson four-junction logic (4JL) gate that serves as a preamplifier. The basic structure is based on our previous design using the 2.5-kA/cm2Nb process. In this study, we optimized the critical current and the load resistance of the 4JL gate, taking into account the parameters of the Josephson junctions in the 10-kA/cm2process. In experiments with the fabricated test circuit, we confirmed the correct operation of the JLD (bit error rate−11) at a target frequency of 5 GHz. We also confirmed the correct function of multichannel JLDs, which were used as interface circuits in Josephson-CMOS hybrid memory, in a low-frequency test.
Superconductor electronics for high-performance computing and high-speed analog-to-digital converters requires multi-channel digital data links. Most difficult is the amplification of the weak signals from the superconductor circuit to the volt level of semiconductor electronics. We developed a hybrid digital interface based on a Josephson latching driver, the so-called Suzuki stack, and a clocked CMOS comparator. The input can be directly triggered by a single flux quantum pulse and the output provides a 1 V CMOS-level signal. In contrast to existing systems, our interface is optimized for ultra-low-power consumption to enable its application for parallel multi-bit data interfaces. We provide evaluation of various types of Suzuki stacks and various CMOS comparators. We present experimental data on the delay of the overall hybrid interface and the total power consumption. The bit-error rate has been measured to be below 10-12. We will discuss the trade-off among circuit robustness, speed, and power consumption.
Abstract Josephson-CMOS hybrid memory leverages the high speed and low power operation of single-flux quantum logic and the high integration densities of CMOS technology. One of the commonly used type of interface circuits in Josephson-CMOS memory is a Suzuki stack, which is a latching high-voltage driver circuit. Suzuki stack circuits are typically powered by an AC bias voltage that has several limitations such as synchronization and coupling effects. To address these issues, a novel DC-biased Suzuki stack circuit is proposed in this paper. As compared to a conventional AC-biased Suzuki stack circuit, the proposed DC-biased design can provide similar output voltage levels and parameter margins, approximately two times higher operating frequency, and three orders of magnitude lower heat load of bias cables.
In this paper, the author describes studies on electronic devices and circuits utilizing both of superconductors and semniconductors. First, a design of an interface circuit composed of Josephson junctions and MOSFETs is described. The Josephson-MOS interface circuit will be used for realizing high-speed data communication between a Josephson digital circuit and a semiconductor one. Second, fabrication and characterization of MOSFETs with superconductive NbN gate electrodes are described. The use of superconductive gates makes it easy to hybridize MOSFETs with Josephson junctions. Finally, studies of Josephson-CMOS hybrid memory circuits are introduced.
Abstract Conventional interfaces for a Josephson-CMOS hybrid system typically rely on Josephson latching drivers (JLDs) or SQUID (Superconducting Quantum InterferenceDevice) stacks to convert weak signals, which are then connected to additional amplifiers providing outputs of 1.2 V or 1.8 V. JLDs output tens of millivolts but require AC bias and precise clock alignment. SQUID stacks reach frequencies of tens of GHz but output few millivolts voltages and occupy large area. To address these challenges, an interface based on SiGe BiCMOS(Silicon-Germanium Bipolar Complementary Metal-Oxide-Semiconductor) has been designed, fabricated, and tested. Fabricated using the 130 nm SiGe BiCMOS process, the interface converts 200 μV voltage signals to 1.2 V and consumes only 386 μW per channel at 4.2 K. In low-frequency measurement, the hybrid system supports 21-channel signals conversion without requiring additional CMOS amplifiers, simplifying cryogenic system design. Advantages include eliminating the need for AC bias and clock alignment, while drawbacks like limited speed are also discussed. This technology facilitates the practical application of multichannel superconducting computers and other applications that require efficient signal conversion, making it one of the most promising interface solutions for the hybrid system.
Results of an experiment on Josephson-CMOS memories show that these circuits have the potential to remove the memory bottleneck faced by superconductive electronics and the speed limitations of purely CMOS memories. The experiment demonstrates monolithic integrated Nb-AlO/sub x/-Nb Josephson-CMOS digital circuits operating at 4 K, the feasibility of Josephson-CMOS interface circuits with conversion delays of less than 150 ps, and fluxoelectronic current sensing of MOS RAM and CAM (content-addressable memory) cells using 4JL gates and SQUIDs (superconducting quantum interference devices).>