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Applied Physics Letters

Sub-μm, planarized, Nb-AlOx-Nb Josephson process for 125 mm wafers developed in partnership with Si technology

M. B. Ketchen, Dale J. Pearson, Alan W. Kleinsasser, Chunhua Hu, M. Smyth, John R. Logan, Kevin G. Stawiasz, E. Baran, Mark A. Jaso, T. Ross, Karen E. Petrillo, M. P. Manny, S. Basavaiah, S. Brodsky, Steven B. Kaplan, W. J. Gallagher, Manjul Bhushan

Published Nov 11, 1991• 107 citations
Publisher

Abstract

We have demonstrated a new planarized all-refractory technology for low Tc superconductivity (PARTS). With the exception of the Nb-AlOx-Nb trilayer preparation, the processing is done almost exclusively within an advanced Si technology fabrication facility. This approach has allowed us to leverage highly off of existing state-of-the-art lithography, metal etching, materials deposition, and planarization capabilities. Using chemical-mechanical polish as the planarization technique we have fabricated Josephson junctions ranging in size from 0.5–100 μm2. Junction quality is excellent with the figure of merit Vm typically exceeding 70 mV. PARTS has yielded fully functional integrated Josephson devices including magnetometers, gradiometers, and soliton oscillators.

DOI
10.1063/1.106405

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arXiv:1210.1012•IEEE Transactions on Applied Superconductivity•Dec 4, 2012•11 citations
We have demonstrated a new planarized all-refractory technology for low Tc superconductivity (PARTS). With the exception of the Nb-AlOx-Nb trilayer preparation, the processing is done almost exclusively within an advanced Si technology fabrication facility. This approach has allowed us to leverage highly off of existing state-of-the-art lithography, metal etching, materials deposition, and planarization capabilities. Using chemical-mechanical polish as the planarization technique we have fabricated Josephson junctions ranging in size from 0.5–100 μm2. Junction quality is excellent with the figure of merit Vm typically exceeding 70 mV. PARTS has yielded fully functional integrated Josephson devices including magnetometers, gradiometers, and soliton oscillators.
A trilayer deposition process for making high quality all-refractory Nb/AlOx/Nb Josephson junctions is described. The sputtering parameters were optimized to deposit very uniform Al films, less than 5 nm in thickness. We found that it was essential to keep the substrate temperature below 40 °C during Al deposition but not during Nb depositions. Rapid anodization of the Nb counterelectrode allowed us to use positive photoresist as an anodization mask even for submicron geometries. The dc superconducting quantum interference devices made with this process have the lowest intrinsic energy sensitivity reported to date for an all-refractory technology.
Planarized Process for Single-Flux-Quantum Circuits With Self-Shunted Nb/Nbx_{x}x​Si1−x_{1-x}1−x​/Nb Josephson Junctions
We describe our process for fabricating single-flux-quantum circuits for applications in communications metrology, advanced computing, and quantum information. The process flow includes four superconducting metal layers, one junction layer, one palladium-gold bias resistor layer, and a contact pad layer. Planarization using chemical-mechanical polishing is performed on the two lower insulating layers. This process is based on Josephson junctions with niobium superconducting electrodes and self-shunted, amorphous niobium-doped silicon barriers on the insulating side near the metal-insulator transition. The barrier material is deposited by cosputtering silicon and niobium, with the junction properties controlled by the relative sputtering powers and the duration of the barrier deposition step. The profiles of the deposition rates across 3-in (76.2 mm) wafers give a corresponding radial profile of the critical current density Jcthat increases by ~46% from the center to the edge of the wafer. To characterize our process, we have measured and show data for niobium metal quality and its magnetic penetration depth, as well as for wire and via inductances, and for via critical currents. The uniformity of the junction critical current Icacross a wafer was measured on test chips with 2.7-μm-diameter junctions. Within a 5 mm × 5 mm area, the standard deviation of Icwas ~2% for chips near the center of the wafer and up to ~7% for chips near the edge. We also describe process improvements and innovations under development aimed at increasing circuit density and high-speed performance.
Fabrication And Characterization Of High-Quality Nb/Al-AlOx_xx​/Nb Cross-Type Josephson Tunnel Junctions Utilising CMP-based Planarisation Techniques
Josephson tunnel junctions (JJs) are the fundamental building blocks of today's most advanced superconducting electronic components, such as qubits and superconducting quantum interference devices (SQUIDs). Given the ongoing demand for scalability of these devices on the wafer-scale, it is crucial to control the fabrication process as precisely as possible to ensure uniform quality and reproducibility. Today, window-type JJs are often used in the production of DC SQUIDs and while they are reliable and reproducible, they suffer from alignment inaccuracies caused by photolithography and unavoidable parasitic capacitances, thus limiting the energy sensitivity of DC SQUIDs. These problems can be circumvented by producing JJs with cross-type geometry, which allows for smaller junction areas and eliminates parasitic capacitances. Here we discuss the fabrication of Nb/Al-AlOx/Nb-based cross-type JJs, where the trilayer is embedded in sputter-deposited SiO2_22​ to allow for planarisation of the structures and to ensure the reliable insulation of the sidewalls of the bottom electrode. Instead of lift-off processes that require a lot of time and potentially leave unwanted wings along the edges of microstructures behind that might compromise subsequent layers, we use chemical-mechanical polishing (CMP) for the removal of excess SiO2_22​. This is not only much faster, but produces smooth and uniform surfaces, which in turn effectively improves the reliability of our JJ production process resulting in a high yield of over 90 %90\,\%90% on wafer-scale. In addition, we discuss the influence of fabrication details on the quality and electrical properties of our JJs with different junction areas down to 1 μm×1 μm1\,\mathrm{μm} \times 1\,\mathrm{μm}1μm×1μm distributed across the wafer and extract the junction specific quality parameters from their IV-characteristics and their Fraunhofer patterns.
A simple and robust process for fabricating low-T/sub c/ Josephson junction integrated circuits has been developed. The process is designed around the Nb/Al/sub 2/O/sub 3/-Al/Nb trilayer, and utilized nine masking steps to form two separate levels of trilayer Josephson junctions, as well as resistors, capacitors, and transmission lines. Materials used for interlayer dielectrics and passivation layers are silicon dioxide and silicon nitride formed by plasma-enhanced chemical vapor deposition (PECVD). The PECVD equipment yields a high deposition rate at moderate substrate temperatures. No degradation of the junction characteristics due to these depositions is seen. The measured loss tangent of this dielectric at 10 GHz using a parallel plate technique is 4.44*10/sup -4/. The dielectric constant of this material is 5.1 in the range of 50 to 400 GHz, measured using an on-chip resonator capacitively coupled to a single shunted Josephson junction. The physical quality of the oxide has been investigated using a variety of tests and has proven to be excellent. A variety of simple circuits using this process technology have been fabricated and tested. More complex circuits are currently under development.
Sub-μm\mu\hbox{m}μm Josephson Junctions for Superconducting Quantum Devices
For high-performance superconducting quantum devices based on Josephson junctions (JJs), decreasing lateral sizes is of great importance. Fabrication of sub-μm JJs is challenging, due to nonflat surfaces with step heights of up to several 100 nm generated during the fabrication process. We have refined a fabrication process with significantly decreased film thicknesses, resulting in almost flat surfaces at intermediate steps during the JJ definition. In combination with a mix-and-match process, combining electron-beam lithography and conventional photolithography, we can fabricate JJs with lateral dimensions down to 0.023 μm2. We propose this refined process as an alternative to the commonly used chemical-mechanical polishing procedure. Transport measurements of JJs, having critical-current densities ranging from 50 to 104A/cm2, are presented at 4.2 K. Our JJ process yields excellent quality parameters, Rsg/RNup to ~ 50, Vmfrom 15 to 80 mV and Vgapup to 2.81 mV, and also allows the fabrication of high-quality, sub-μm wide, long JJs (LJJs) for the study of Josephson vortex behavior. The developed technique can also be used for similar multilayer processes and is very promising for fabricating sub- μm JJs for quantum devices such as SQUIDs, qubits, and SIS mixers.