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IEEE Transactions on Applied Superconductivity

Contention solver for a superconducting packet switch

M. Hosoya, S. Kominami, W. Hioe, T. Nishino

Published Jun 1, 1997• 5 citations
Publisher

Abstract

The paper describes the architecture of a contention solver (CS) to be used in a superconducting packet switch prototype, and the design and tests of 2/spl times/2 switching elements which compose the CS. The contention solver is based on a Batcher sorter, in which switching elements check for contention between input packets. A priority port is used to guarantee correct operation of the sorter even if a packet is invalidated during the sorting process. A 2/spl times/2 CS switching element with 2-bit data-width was designed in dual-rail logic. It was fabricated using three-junction SQUID gates by a standard Nb tri-layer process, and consists of 102 OR-equivalent gates in an area of 1.2 mm x 1.8 mm. Its correct operation was confirmed completely.

DOI
10.1109/77.621692

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The paper describes the architecture of a contention solver (CS) to be used in a superconducting packet switch prototype, and the design and tests of 2/spl times/2 switching elements which compose the CS. The contention solver is based on a Batcher sorter, in which switching elements check for contention between input packets. A priority port is used to guarantee correct operation of the sorter even if a packet is invalidated during the sorting process. A 2/spl times/2 CS switching element with 2-bit data-width was designed in dual-rail logic. It was fabricated using three-junction SQUID gates by a standard Nb tri-layer process, and consists of 102 OR-equivalent gates in an area of 1.2 mm x 1.8 mm. Its correct operation was confirmed completely.
The paper introduces a prototype model of a superconducting packet switch which is composed of an input buffer, a contention solver, and a distribution network. The input buffer and the contention solver enable contention-free distribution of data packets. The total design of the prototype has been completed and the total operation has been numerically simulated and confirmed. A 2/spl times/2 switching element which controls the paths of two packets is the key component of the prototype. The basic switching element with 1-b data-width is fabricated by a standard Nb trilayer process. Three-junction SQUIDs driven by a three-phase powering clock are used in the switch. The correct operation up to 3.5 GHz, limited by the measurement setup, is confirmed. The margin evaluation shows there remains enough margin at GHz operations.
The paper describes a Batcher sorter and a Banyan network which together form a nonblocking and self-routing switch. The Batcher sorter sorts input packets in the order of their address values. This sorting operation guarantees no blocking in the succeeding Banyan network and presents an efficient way to check contention. The Banyan network distributes contention-free packets to their final destinations. The Batcher and Banyan switches were designed by using a three-junction SQUID gate family driven by three-phase powering clocks. The Batcher sorter is composed of 2/spl times/2 Batcher switching elements. Each Batcher switching element sorts two input packets in the order of their address values. A 4/spl times/4 Batcher sorter with 2-b data width, which is composed of six 2/spl times/2 Batcher switching elements, was fabricated by an Nb tri-layer process. Its correct operation was confirmed. The Banyan network consists of 2/spl times/2 Banyan switching elements. A 2/spl times/2 Banyan switching element with 2-b data width was also fabricated. The correct operation was confirmed up to 4 GHz by using a test pattern generator integrated on-chip.
A new SFQ data communication switch has been designed and tested. Complete operation of a 4/spl times/4 switch circuit has been demonstrated with address decoding at low-speed. Transmission through a given path in the switch has been demonstrated for data rates up to 4 Gb/s. Circuit simulations show operation of the switch cells up to 30 Gb/s. The circuit was fabricated using HYPRES's standard 1 kA/cm/sup 2/ niobium process. The switch has a crossbar architecture with an RF SQUID based switch cell at each crosspoint. The address is decoded by means of RSFQ shift registers which are integrated into the switch matrix. The design enables high bit-rate, low crosstalk, non-blocking architecture, NRZ or RZ data format, and self routing of variable length data packets.
A single-flux-quantum (SFQ) device provides fast operation with low power consumption. As SFQ devices can be applied in network switches requiring high throughput, we have been developing an SFQ network switch system. Not only the switch fabric but also the switch scheduler is a key component for a high-throughput network switch. The switch scheduler orders multiple inputs to a single output at the same time to prevent collisions from occurring in the switch fabric. The scheduling time becomes longer as the number of switch ports increases, because the scheduler must scan requests from all input ports. We designed two types of 4-port arbiters (i.e. switch scheduler sub-circuits) with structures based on serial or parallel processing. We chose to implement and demonstrate the serial arbiter because it has a smaller number of gates. It consisted of about 1800 Josephson junctions, including on-chip test circuitry. We tested a fabricated circuit at high speed and confirmed its correct operation at 40 GHz.
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A critical component for high bandwidth communications links is a digital switch. Desirable features of a digital switch include: high input/output bandwidth, high channel count, scalability, low latency and interchannel skew. Superconductive circuits, with simultaneous high speed and low power advantages (even including the requisite cryocooler) have been applied to a highly scaleable crossbar switch, useful in supercomputer networks, massively parallel processing (MPP), and high data rate telecommunications. We report here on the testing of a 16/spl times/16 switch chip based on the switch chip component of the highly scaleable crossbar system. We have successfully transmitted multi-Gb/s data through this superconducting switch, with packet destination addressing decoded from the header of the data packet. The data are transmitted to a separate superconducting amplifier chip, mounted on a superconducting multi-chip module with the switch. The switch is a crossbar architecture, voltage state design, and operated to beyond 3 Gb/s. The amplifier is a clocked latching stack of Josephson junctions. Output of the amplifier at 6.2 Gb/s is 7.0 mV, which facilitates the interface of the module to its users. BER of the two-chip assembly is 10/sup -9/ or less above 2 Gb/s.