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IEEE Transactions on Applied Superconductivity

3.5 GHz operation of a superconducting packet switch element

M. Hosoya, W. Hioe, S. Kominami, Hideyuki Nagaishi, T. Nishino

Published Jan 1, 1996• 7 citations
Publisher

Abstract

The paper introduces a prototype model of a superconducting packet switch which is composed of an input buffer, a contention solver, and a distribution network. The input buffer and the contention solver enable contention-free distribution of data packets. The total design of the prototype has been completed and the total operation has been numerically simulated and confirmed. A 2/spl times/2 switching element which controls the paths of two packets is the key component of the prototype. The basic switching element with 1-b data-width is fabricated by a standard Nb trilayer process. Three-junction SQUIDs driven by a three-phase powering clock are used in the switch. The correct operation up to 3.5 GHz, limited by the measurement setup, is confirmed. The margin evaluation shows there remains enough margin at GHz operations.

DOI
10.1109/77.559340

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IEEE Transactions on Applied Superconductivity•Jun 1, 1999•20 citations
The paper introduces a prototype model of a superconducting packet switch which is composed of an input buffer, a contention solver, and a distribution network. The input buffer and the contention solver enable contention-free distribution of data packets. The total design of the prototype has been completed and the total operation has been numerically simulated and confirmed. A 2/spl times/2 switching element which controls the paths of two packets is the key component of the prototype. The basic switching element with 1-b data-width is fabricated by a standard Nb trilayer process. Three-junction SQUIDs driven by a three-phase powering clock are used in the switch. The correct operation up to 3.5 GHz, limited by the measurement setup, is confirmed. The margin evaluation shows there remains enough margin at GHz operations.
The paper describes the architecture of a contention solver (CS) to be used in a superconducting packet switch prototype, and the design and tests of 2/spl times/2 switching elements which compose the CS. The contention solver is based on a Batcher sorter, in which switching elements check for contention between input packets. A priority port is used to guarantee correct operation of the sorter even if a packet is invalidated during the sorting process. A 2/spl times/2 CS switching element with 2-bit data-width was designed in dual-rail logic. It was fabricated using three-junction SQUID gates by a standard Nb tri-layer process, and consists of 102 OR-equivalent gates in an area of 1.2 mm x 1.8 mm. Its correct operation was confirmed completely.
The paper describes a Batcher sorter and a Banyan network which together form a nonblocking and self-routing switch. The Batcher sorter sorts input packets in the order of their address values. This sorting operation guarantees no blocking in the succeeding Banyan network and presents an efficient way to check contention. The Banyan network distributes contention-free packets to their final destinations. The Batcher and Banyan switches were designed by using a three-junction SQUID gate family driven by three-phase powering clocks. The Batcher sorter is composed of 2/spl times/2 Batcher switching elements. Each Batcher switching element sorts two input packets in the order of their address values. A 4/spl times/4 Batcher sorter with 2-b data width, which is composed of six 2/spl times/2 Batcher switching elements, was fabricated by an Nb tri-layer process. Its correct operation was confirmed. The Banyan network consists of 2/spl times/2 Banyan switching elements. A 2/spl times/2 Banyan switching element with 2-b data width was also fabricated. The correct operation was confirmed up to 4 GHz by using a test pattern generator integrated on-chip.
We have been developing a single-flux-quantum (SFQ) cross-bar switch, which is a main component of a network packet switch. We think that a network switch is an application in which the high speed of SFQ technology would be advantageous. Anticipating general and large-scale SFQ logic circuit design, we used the cell-based design method and the CONNECT standard SFQ cell library. The two-input and two-output cross-bar switch, a core switch component, consists of 13 logic cells connected by Josephson-transmission-line (JTL) cells. Because of the large size of JTL cells and the large delay in them, timing adjustment becomes more difficult as the operating speed and circuit size increase. After using a commercially available automatic router to find appropriate routes efficiently, we used a static timing analyzer for fine timing adjustment. Timing violations were fixed by changing JTL path delays using the tools we developed. The target operating frequency of the switch was 40 GHz, which corresponds to a clock period of 25 ps. Careful timing adjustment was necessary to ensure correct operations at such a high speed. The test chip was fabricated by using an NEC standard Nb process. The circuit, including on-chip test circuitry, was composed of about 1500 Josephson junctions. We confirmed its correct operations up to 50 GHz with a bias margin of /spl plusmn/20%.
We report on the first complete system-level demonstration of a superconducting digital communication system. In today's digital computer and communication systems, managing data flow is a major challenge as the systems have to deal with a huge amount of information. A superconductor device may solve this problem. There have been several attempts to make superconducting switching core circuits, but there have been no complete system-level demonstrations. We have built such a system to demonstrate the efficiency of superconducting devices used in a communication system. Our system is focused on parallel processor communication, and consists of PCs as the processor elements at the three nodes, three interface boxes, and a superconductive chip immersed in a 4.2-K cryostat. The interconnection chip operation is essentially packet switching that was designed with a pipeline ring architecture. The interface box consists of parallel-serial converters, serial-parallel converters, a FIFO output buffer, and a level conversion circuit. The network system operates successfully at approximately 100 MHz, and the clock frequency is restricted by the speed of the interface ICs, not by that of the superconductive chip. We also confirmed the 2-GHz operation of the switching chip, and estimate that the total throughput of the system ran be increased to more than 10 Gbps.
We have designed a speedup buffer (SB) that is indispensable for realizing a high-throughput network switch based on single-flux-quantum (SFQ) technology. The SB performs the rate conversion from 10 to 40 Gbps for the packet data streams fed into the Banyan switch. This approach can reduce the packet-blocking rate, resulting in an increased throughput for the network switch. The SB is composed of a 1:3 stream demultiplexer (SDMUX), three variable-bit-length shift registers (VLSRs) and a 3:1 stream multiplexer, coupled with a controller. We have successfully demonstrated the 1:3 SDMUX and the VLSR. As for the VLSR, we confirmed high-speed operation up to 55 GHz. We have also designed the SB using these components. The SB is a large-scale circuit composed of 11 663 Josephson junctions on a 3.8 × 3.8 mm 2 area. So far, partial operations have been demonstrated experimentally.
A critical component for high bandwidth communications links is a digital switch. Desirable features of a digital switch include: high input/output bandwidth, high channel count, scalability, low latency and interchannel skew. Superconductive circuits, with simultaneous high speed and low power advantages (even including the requisite cryocooler) have been applied to a highly scaleable crossbar switch, useful in supercomputer networks, massively parallel processing (MPP), and high data rate telecommunications. We report here on the testing of a 16/spl times/16 switch chip based on the switch chip component of the highly scaleable crossbar system. We have successfully transmitted multi-Gb/s data through this superconducting switch, with packet destination addressing decoded from the header of the data packet. The data are transmitted to a separate superconducting amplifier chip, mounted on a superconducting multi-chip module with the switch. The switch is a crossbar architecture, voltage state design, and operated to beyond 3 Gb/s. The amplifier is a clocked latching stack of Josephson junctions. Output of the amplifier at 6.2 Gb/s is 7.0 mV, which facilitates the interface of the module to its users. BER of the two-chip assembly is 10/sup -9/ or less above 2 Gb/s.