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IEEE Transactions on Applied Superconductivity

SFQ data communication switch

Noshir Dubash, Perng-Fei Yuh, V. Borzenets, T. Van Duzer, Stephen R. Whiteley

Published Jun 1, 1997• 14 citations
Publisher

Abstract

A new SFQ data communication switch has been designed and tested. Complete operation of a 4/spl times/4 switch circuit has been demonstrated with address decoding at low-speed. Transmission through a given path in the switch has been demonstrated for data rates up to 4 Gb/s. Circuit simulations show operation of the switch cells up to 30 Gb/s. The circuit was fabricated using HYPRES's standard 1 kA/cm/sup 2/ niobium process. The switch has a crossbar architecture with an RF SQUID based switch cell at each crosspoint. The address is decoded by means of RSFQ shift registers which are integrated into the switch matrix. The design enables high bit-rate, low crosstalk, non-blocking architecture, NRZ or RZ data format, and self routing of variable length data packets.

DOI
10.1109/77.621791

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A new SFQ data communication switch has been designed and tested. Complete operation of a 4/spl times/4 switch circuit has been demonstrated with address decoding at low-speed. Transmission through a given path in the switch has been demonstrated for data rates up to 4 Gb/s. Circuit simulations show operation of the switch cells up to 30 Gb/s. The circuit was fabricated using HYPRES's standard 1 kA/cm/sup 2/ niobium process. The switch has a crossbar architecture with an RF SQUID based switch cell at each crosspoint. The address is decoded by means of RSFQ shift registers which are integrated into the switch matrix. The design enables high bit-rate, low crosstalk, non-blocking architecture, NRZ or RZ data format, and self routing of variable length data packets.
A critical component for high bandwidth communications links is a digital switch. Desirable features of a digital switch include: high input/output bandwidth, high channel count, scalability, low latency and interchannel skew. Superconductive circuits, with simultaneous high speed and low power advantages (even including the requisite cryocooler) have been applied to a highly scaleable crossbar switch, useful in supercomputer networks, massively parallel processing (MPP), and high data rate telecommunications. We report here on the testing of a 16/spl times/16 switch chip based on the switch chip component of the highly scaleable crossbar system. We have successfully transmitted multi-Gb/s data through this superconducting switch, with packet destination addressing decoded from the header of the data packet. The data are transmitted to a separate superconducting amplifier chip, mounted on a superconducting multi-chip module with the switch. The switch is a crossbar architecture, voltage state design, and operated to beyond 3 Gb/s. The amplifier is a clocked latching stack of Josephson junctions. Output of the amplifier at 6.2 Gb/s is 7.0 mV, which facilitates the interface of the module to its users. BER of the two-chip assembly is 10/sup -9/ or less above 2 Gb/s.
We describe the design of a fast single-flux-quantum decoder which can be used, e.g., in fast RAMs, general-purpose microprocessors, and communication channel switches. The core of the circuit is a tree of the single-bit SFQ demultiplexer with toggle (rather than the reset-set) control. Three new RSFQ cells: the demultiplexer, D flip-flop with complementary outputs, and serial XOR with large parameter tolerances (dc bias margins of /spl plusmn/25%, /spl plusmn/26%, and /spl plusmn/27%, respectively) have been developed for the decoder project. We have designed the first 16-bit prototype of the decoder for 1-kA/cm/sup 2/ niobium-trilayer technology and tested it at low frequencies. The circuit was completely operable except for 3 (of 16) output SFQ/DC converters. Simulations show that the circuit should allow data rate in excess of 60 Gbit/s and channel switching time below 20 ps.>
The lack of a high-density and high-speed memory is a serious impediment for realization of large-scale RSFQ digital systems. A shift resister memory, which has high throughput and simple circuit structure, is one candidate to overcome this drawback. We show a design framework of the shift register memory, which is usable for the high-speed register files and the main memories of the RSFQ microprocessor. The proposed system consists of an array of shift registers and a packet decoder that switches a high-speed serial data stream into the specified shift register. The target clock frequency is 16 GHz assuming 2.5 kA/cm/sup 2/ Nb standard process. We have estimated the propagation delay and the circuit area of the data-driven self-timed (DDST) packet decoder. Based on this estimation, we have also evaluated the access time and the area of the memory system. Several key components, including the one-to-two packet switch and the one-to-four DDST packet decoder, were implemented and their correct operations were confirmed.
A crossbar switch has been designed using Single Flux Quantum (SFQ) gates exclusively for all internal functions. A 4/spl times/4 prototype has been fabricated in our Nb process foundry with J/sub c/ of 2000 A/cm/sup 2/. We report on the design and performance of the switch and of an individual crosspoint element at high data rates (/spl ges/1 Gbps). A novel design of a double-edge-triggered dc/SFQ converter is discussed. The requirements for output amplification and on-chip versus off-chip amplifier issues will be presented.
We have been developing a single-flux-quantum (SFQ) cross-bar switch, which is a main component of a network packet switch. We think that a network switch is an application in which the high speed of SFQ technology would be advantageous. Anticipating general and large-scale SFQ logic circuit design, we used the cell-based design method and the CONNECT standard SFQ cell library. The two-input and two-output cross-bar switch, a core switch component, consists of 13 logic cells connected by Josephson-transmission-line (JTL) cells. Because of the large size of JTL cells and the large delay in them, timing adjustment becomes more difficult as the operating speed and circuit size increase. After using a commercially available automatic router to find appropriate routes efficiently, we used a static timing analyzer for fine timing adjustment. Timing violations were fixed by changing JTL path delays using the tools we developed. The target operating frequency of the switch was 40 GHz, which corresponds to a clock period of 25 ps. Careful timing adjustment was necessary to ensure correct operations at such a high speed. The test chip was fabricated by using an NEC standard Nb process. The circuit, including on-chip test circuitry, was composed of about 1500 Josephson junctions. We confirmed its correct operations up to 50 GHz with a bias margin of /spl plusmn/20%.
4/spl times/4 single-flux-quantum (SFQ) network switch has been packaged and successfully demonstrated in a hybrid closed-cycle refrigerator (CCR) system at multigigabit data rates. Full operation of the packaged switch, with self-routing of 1-Gb/s data packets, was demonstrated using a 1-GHz address header decode. The switch is packaged on a superconducting multichip module (MCM) mounted on the 4.5-K stage of the CCR. On-chip asynchronous Josephson drivers and cooled GaAs preamplifiers are used to amplify the SFQ outputs of the switch. The maximum operation bandwidth of the switch is currently limited by the asynchronous Josephson driver. New designs of the Josephson drivers, which have demonstrated operation at 10 Gb/s, are expected to enable switch operation at 10 Gb/s. The system is equipped with fiber-optical inputs and high-speed cryogenic photodetectors. The fiber-optic interfaces, RF packaging, and MCM packaging in the CCR system have demonstrated error-free operation at 10 Gb/s.