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IEEE Transactions on Applied Superconductivity

Single flux quantum crossbar switch

Qing Ke, Bruce J. Dalrymple, D.J. Durand, J.W. Spargo

Published Jun 1, 1997• 13 citations
Publisher

Abstract

A crossbar switch has been designed using Single Flux Quantum (SFQ) gates exclusively for all internal functions. A 4/spl times/4 prototype has been fabricated in our Nb process foundry with J/sub c/ of 2000 A/cm/sup 2/. We report on the design and performance of the switch and of an individual crosspoint element at high data rates (/spl ges/1 Gbps). A novel design of a double-edge-triggered dc/SFQ converter is discussed. The requirements for output amplification and on-chip versus off-chip amplifier issues will be presented.

DOI
10.1109/77.621939

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IEEE Transactions on Applied Superconductivity•Jun 1, 2005•27 citations
A crossbar switch has been designed using Single Flux Quantum (SFQ) gates exclusively for all internal functions. A 4/spl times/4 prototype has been fabricated in our Nb process foundry with J/sub c/ of 2000 A/cm/sup 2/. We report on the design and performance of the switch and of an individual crosspoint element at high data rates (/spl ges/1 Gbps). A novel design of a double-edge-triggered dc/SFQ converter is discussed. The requirements for output amplification and on-chip versus off-chip amplifier issues will be presented.
A single-flux-quantum (SFQ) device provides fast operation with low power consumption. As SFQ devices can be applied in network switches requiring high throughput, we have been developing an SFQ network switch system. Not only the switch fabric but also the switch scheduler is a key component for a high-throughput network switch. The switch scheduler orders multiple inputs to a single output at the same time to prevent collisions from occurring in the switch fabric. The scheduling time becomes longer as the number of switch ports increases, because the scheduler must scan requests from all input ports. We designed two types of 4-port arbiters (i.e. switch scheduler sub-circuits) with structures based on serial or parallel processing. We chose to implement and demonstrate the serial arbiter because it has a smaller number of gates. It consisted of about 1800 Josephson junctions, including on-chip test circuitry. We tested a fabricated circuit at high speed and confirmed its correct operation at 40 GHz.
We describe the design of a fast single-flux-quantum decoder which can be used, e.g., in fast RAMs, general-purpose microprocessors, and communication channel switches. The core of the circuit is a tree of the single-bit SFQ demultiplexer with toggle (rather than the reset-set) control. Three new RSFQ cells: the demultiplexer, D flip-flop with complementary outputs, and serial XOR with large parameter tolerances (dc bias margins of /spl plusmn/25%, /spl plusmn/26%, and /spl plusmn/27%, respectively) have been developed for the decoder project. We have designed the first 16-bit prototype of the decoder for 1-kA/cm/sup 2/ niobium-trilayer technology and tested it at low frequencies. The circuit was completely operable except for 3 (of 16) output SFQ/DC converters. Simulations show that the circuit should allow data rate in excess of 60 Gbit/s and channel switching time below 20 ps.>
We demonstrated the 4 /spl times/ 4-cross/bar-40 Gbps/ch switch which is functionally compatible with a commercial semiconductor one in order to evaluate the current SFQ circuit technology quantitatively in both a operating speed and power consumption. According to our numerical simulations, the SFQ switch has one or two orders of magnitude higher throughput per a single channel than that of the semiconductor, and has much smaller exchanging times between routing paths. In an actual test based on the NEC Nb-2.5 kA/cm/sup 2/ junction technology, correct operation using an on-chip test system made up of 4700 Josephson junctions was confirmed up to 37 Gbps/ch which is about 14 times faster than the semiconductor of 2.7 Gbps/ch speed. We also confirmed that SFQ circuits consumed 1/800 power compared with those of semiconductor. The reason why data rates obtained experimentally did not reach the designed speed of 40 Gbps/ch is due to both the timing error and the influence of magnetic fields caused by large bias currents exceeding 500 mA. These results of quantitative evaluation show that the SFQ technology has much greater potentials than the semiconductor one in both the operating speed and the power consumption, which means it is very effective to apply the SFQ technology to digital applications.
We have designed and measured single flux quantum (SFQ) circuits for data switching at 2.5 Gbps. A fully functional 2/spl times/2 switching node is presented. The node can be used to form a larger switching fabric (4/spl times/4, 8/spl times/8, etc.). The node accepts data streams at either or both inputs, routing the data based on address bits present in the data stream. This approach allows the data to be self-routing and the switch to be self-synchronous. In addition, the switch can route data correctly on an active input line if the other is idle.
A suitable data link from RSFQ to semiconductor electronics remains challenging. We report an output amplifier that uses a new pulse multiplier circuit. The pulse multiplier consists of several stages arranged in series; a double-flux-quantum gate at each stage promotes the SFQ pulse to the next stage. Characteristics of the circuit design are: 1) DC power. As with the DFQ gate, every unshunted Josephson junction in the amplifier is loaded by critically-damped junctions that prevent voltage-state modes. 2) Equal rise and fall times that scale with output amplitude. In our case, 50 ps rise and fall time and 1-2 mV output amplitude can be realized, which is ideal for a data rate of 10 Gb/s. 3) Quantum accurate voltage multiplication independent of bias current. 4) Non-return-to-zero (NRZ) operation. The circuit was designed and successfully tested in our 8 kA/cm/sup 2/ foundry process. A 60 GHz pulse train, generated on-chip, was gated with RSFQ logic to produce a data pattern that was then fed into a pulse multiplier of either ten or twenty stages. Voltage multiplication was observed with operating margins of /spl plusmn/21% on bias current. Fast rise time was directly observed; unfortunately, fall time was spoiled by ringing on a 1 ns time scale. It is plausible that small changes to the physical layout of the circuit would produce desired operation.