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IEEE Transactions on Applied Superconductivity

Quantitative Evaluation of the Single-Flux- Quantum Cross/Bar Switch

Takahiro Yamada, Masato Yoshida, T. Hanai, Akira Fujimaki, Hisao Hayakawa, Y. Kameda, Shinichi Yorozu, Hirotaka Terai, Nobuyuki Yoshikawa

Published Jun 1, 2005• 11 citations

Abstract

We demonstrated the 4 /spl times/ 4-cross/bar-40 Gbps/ch switch which is functionally compatible with a commercial semiconductor one in order to evaluate the current SFQ circuit technology quantitatively in both a operating speed and power consumption. According to our numerical simulations, the SFQ switch has one or two orders of magnitude higher throughput per a single channel than that of the semiconductor, and has much smaller exchanging times between routing paths. In an actual test based on the NEC Nb-2.5 kA/cm/sup 2/ junction technology, correct operation using an on-chip test system made up of 4700 Josephson junctions was confirmed up to 37 Gbps/ch which is about 14 times faster than the semiconductor of 2.7 Gbps/ch speed. We also confirmed that SFQ circuits consumed 1/800 power compared with those of semiconductor. The reason why data rates obtained experimentally did not reach the designed speed of 40 Gbps/ch is due to both the timing error and the influence of magnetic fields caused by large bias currents exceeding 500 mA. These results of quantitative evaluation show that the SFQ technology has much greater potentials than the semiconductor one in both the operating speed and the power consumption, which means it is very effective to apply the SFQ technology to digital applications.

DOI: 10.1109/tasc.2005.849819

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Single-flux-quantum (SFQ) technology is a novel technology where binary information is represented by a single flux. It enables us to realize high-speed, low-power SFQ logic circuits, surpassing conventional complementary metal-oxide-silicon (CMOS) technology. We proposed an SFQ packet switch to avoid the bottlenecks in broadband networks of the future. To demonstrate high-speed operation of an SFQ logic circuit and its application to our switch architecture, we designed a cross/bar switch. It consists of 13 logic gates and 581 Josephson junctions were used in the layout. We confirmed correct operations up to 33 GHz in simulation. We placed the switch circuit in an on-chip test system for high-speed (over 10 GHz) test. Including I/O circuits, the system as a whole consists of 1236 Josephson junctions. The chip was fabricated by using NEC's standard Nb process. We carried out an on-chip test and found correct operations up to 35 GHz.

We have been developing a single-flux-quantum (SFQ) cross-bar switch, which is a main component of a network packet switch. We think that a network switch is an application in which the high speed of SFQ technology would be advantageous. Anticipating general and large-scale SFQ logic circuit design, we used the cell-based design method and the CONNECT standard SFQ cell library. The two-input and two-output cross-bar switch, a core switch component, consists of 13 logic cells connected by Josephson-transmission-line (JTL) cells. Because of the large size of JTL cells and the large delay in them, timing adjustment becomes more difficult as the operating speed and circuit size increase. After using a commercially available automatic router to find appropriate routes efficiently, we used a static timing analyzer for fine timing adjustment. Timing violations were fixed by changing JTL path delays using the tools we developed. The target operating frequency of the switch was 40 GHz, which corresponds to a clock period of 25 ps. Careful timing adjustment was necessary to ensure correct operations at such a high speed. The test chip was fabricated by using an NEC standard Nb process. The circuit, including on-chip test circuitry, was composed of about 1500 Josephson junctions. We confirmed its correct operations up to 50 GHz with a bias margin of /spl plusmn/20%.

A single-flux-quantum (SFQ) device provides fast operation with low power consumption. As SFQ devices can be applied in network switches requiring high throughput, we have been developing an SFQ network switch system. Not only the switch fabric but also the switch scheduler is a key component for a high-throughput network switch. The switch scheduler orders multiple inputs to a single output at the same time to prevent collisions from occurring in the switch fabric. The scheduling time becomes longer as the number of switch ports increases, because the scheduler must scan requests from all input ports. We designed two types of 4-port arbiters (i.e. switch scheduler sub-circuits) with structures based on serial or parallel processing. We chose to implement and demonstrate the serial arbiter because it has a smaller number of gates. It consisted of about 1800 Josephson junctions, including on-chip test circuitry. We tested a fabricated circuit at high speed and confirmed its correct operation at 40 GHz.

High-speed logic operation of an output interface circuit for a single-flux-quantum (SFQ) system was demonstrated at a data rate of 5 Gb/s. Using NEC's 2.5-kA/cm/sup 2/ Nb junction process, we designed, fabricated, and tested the interface circuit consisting of a 2-b SFQ demultiplexer and two Josephson latching drivers. We verified the proper operation of the demultiplexer. The interface can convert 5-Gb/s SFQ-pulse data into two-channel 2.5-Gb/s return-to-zero data with an amplitude of approximately 6 mV.

Single flux quantum (SFQ) electronics is extremely fast and has very low on-chip power dissipation. SFQ VLSI is an excellent candidate for high-performance computing and other applications requiring extremely high-speed signal processing. Despite this, SFQ technology has generally not been accepted for system implementation. We argue that this is due, at least in part, to the use of outdated tools to produce SFQ circuits and chips. Assuming the use of tools equivalent to those employed in the semiconductor industry, we estimate the density of Josephson junctions, circuit speed, and power dissipation that could be achieved with SFQ technology. Today, CMOS lithography is at 90?65?nm with about 20 layers. Assuming equivalent technology, aggressively increasing the current density above 100?kA?cm?2 to achieve junction speeds approximately 1000?GHz, and reducing device footprints by converting device profiles from planar to vertical, one could expect to integrate about 250?M Josephson junctions cm?2 into SFQ digital circuits. This should enable circuit operation with clock frequencies above 200?GHz and place approximately 20?K gates within a radius of one clock period. As a result, complete microprocessors, including integrated memory registers, could be fabricated on a single chip.