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Superconductor Science and Technology

High throughput Tandem-Banyan network switch based on SFQ technology

Hirotaka Terai, 義男 亀田, Shinichi Yorozu, Zhen Wang

Published Nov 21, 2001• 5 citations
Publisher

Abstract

A Tandem-Banyan network switch (TBNS) based on superconductor single-flux-quantum technologies is described. Its switching core consists of multiple Banyan networks and transmission checkers (TMCs) connected sequentially. Numerical simulation demonstrated that the maximum throughput of TBNS is much higher than that of the input-buffer-type Batcher-Banyan network switch, while the amount of hardware is comparable with that of a Batcher-Banyan network switch. The two-bit code extraction part of the address decoder of the TMC circuit was designed and implemented using the SFQ cell library developed for NEC Nb standard fabrication process. The correct logic operation was experimentally observed with a bias margin of around ±10%. This switch is suitable for managing the huge amount of data traffic that will be carried in future backbone networks.

DOI
10.1088/0953-2048/14/12/317

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Japanese Journal of Applied Physics•Apr 30, 2003•8 citations
A Tandem-Banyan network switch (TBNS) based on superconductor single-flux-quantum technologies is described. Its switching core consists of multiple Banyan networks and transmission checkers (TMCs) connected sequentially. Numerical simulation demonstrated that the maximum throughput of TBNS is much higher than that of the input-buffer-type Batcher-Banyan network switch, while the amount of hardware is comparable with that of a Batcher-Banyan network switch. The two-bit code extraction part of the address decoder of the TMC circuit was designed and implemented using the SFQ cell library developed for NEC Nb standard fabrication process. The correct logic operation was experimentally observed with a bias margin of around ±10%. This switch is suitable for managing the huge amount of data traffic that will be carried in future backbone networks.
We have carried out a paper feasibility study of the implementation of most common packet switching cores (crossbar, Batcher-banyan, time-division shared bus, and token ring) using the superconductor rapid single flux quantum (RSFQ) digital technology. According to our estimates, the best performance-to-complexity ratio may be obtained for the Batcher-banyan network. For example, a 128 by 128 switching core with self-routing (but without address translation, contention resolution, and broadcast features), consisting of about 180,000 Josephson junctions with the internal clock frequency of 60 GHz could handle a workload of 7.5 Tbps. This core could fit on a single 1 cm by 1 cm chip and dissipate as low as 45 mW. The estimated parameters are achievable using a simple 1.5-micrometer niobium- trilayer technology.
We are developing a single-flux-quantum (SFQ) packet switch for over 1-Tb/s switching systems. Investigation of several switch topologies leads us to select the Batcher-Banyan packet switch because of its simplicity and regularity. The packet switch structure we propose consists of simple 2/spl times/2 unit switches each connected by speeded-up internal links. Numeric simulation showed that the speeded-up links greatly improved the throughput by resolving packet blocking, which is a major drawback of the Banyan switch. High throughput compatible to a crossbar switch was attained by using links whose speed was quadrupled. Moreover, the throughput did not decrease even though the number of input/output ports increased. Taking the speed of SFQ basic gates into account, the cycle time of the 2/spl times/2 unit switch reaches 25 ps, which is sufficient to achieve the 40-GHz operation. If unit switches are connected by quadrupled internal links, the Batcher-Banyan switch can accept the 10-Gb/s external input rate per channel. This indicates that the total throughput of a 128/spl times/128 switch exceeds 1 Tb/s. The unit switch was designed down to the SFQ gate level. To design a large SFQ circuit, we built several "standard" SFQ cells whose shape was square or rectangular with a unit width and height. Such shapes make it easier to place and connect a number of cells. We show some experimental results of testing SFQ standard cells and logic circuits.
We have been developing a single-flux-quantum (SFQ) cross-bar switch, which is a main component of a network packet switch. We think that a network switch is an application in which the high speed of SFQ technology would be advantageous. Anticipating general and large-scale SFQ logic circuit design, we used the cell-based design method and the CONNECT standard SFQ cell library. The two-input and two-output cross-bar switch, a core switch component, consists of 13 logic cells connected by Josephson-transmission-line (JTL) cells. Because of the large size of JTL cells and the large delay in them, timing adjustment becomes more difficult as the operating speed and circuit size increase. After using a commercially available automatic router to find appropriate routes efficiently, we used a static timing analyzer for fine timing adjustment. Timing violations were fixed by changing JTL path delays using the tools we developed. The target operating frequency of the switch was 40 GHz, which corresponds to a clock period of 25 ps. Careful timing adjustment was necessary to ensure correct operations at such a high speed. The test chip was fabricated by using an NEC standard Nb process. The circuit, including on-chip test circuitry, was composed of about 1500 Josephson junctions. We confirmed its correct operations up to 50 GHz with a bias margin of /spl plusmn/20%.
We have designed a speedup buffer (SB) that is indispensable for realizing a high-throughput network switch based on single-flux-quantum (SFQ) technology. The SB performs the rate conversion from 10 to 40 Gbps for the packet data streams fed into the Banyan switch. This approach can reduce the packet-blocking rate, resulting in an increased throughput for the network switch. The SB is composed of a 1:3 stream demultiplexer (SDMUX), three variable-bit-length shift registers (VLSRs) and a 3:1 stream multiplexer, coupled with a controller. We have successfully demonstrated the 1:3 SDMUX and the VLSR. As for the VLSR, we confirmed high-speed operation up to 55 GHz. We have also designed the SB using these components. The SB is a large-scale circuit composed of 11 663 Josephson junctions on a 3.8 × 3.8 mm 2 area. So far, partial operations have been demonstrated experimentally.
The paper describes a Batcher sorter and a Banyan network which together form a nonblocking and self-routing switch. The Batcher sorter sorts input packets in the order of their address values. This sorting operation guarantees no blocking in the succeeding Banyan network and presents an efficient way to check contention. The Banyan network distributes contention-free packets to their final destinations. The Batcher and Banyan switches were designed by using a three-junction SQUID gate family driven by three-phase powering clocks. The Batcher sorter is composed of 2/spl times/2 Batcher switching elements. Each Batcher switching element sorts two input packets in the order of their address values. A 4/spl times/4 Batcher sorter with 2-b data width, which is composed of six 2/spl times/2 Batcher switching elements, was fabricated by an Nb tri-layer process. Its correct operation was confirmed. The Banyan network consists of 2/spl times/2 Banyan switching elements. A 2/spl times/2 Banyan switching element with 2-b data width was also fabricated. The correct operation was confirmed up to 4 GHz by using a test pattern generator integrated on-chip.
Single-flux-quantum (SFQ) technology is a novel technology where binary information is represented by a single flux. It enables us to realize high-speed, low-power SFQ logic circuits, surpassing conventional complementary metal-oxide-silicon (CMOS) technology. We proposed an SFQ packet switch to avoid the bottlenecks in broadband networks of the future. To demonstrate high-speed operation of an SFQ logic circuit and its application to our switch architecture, we designed a cross/bar switch. It consists of 13 logic gates and 581 Josephson junctions were used in the layout. We confirmed correct operations up to 33 GHz in simulation. We placed the switch circuit in an on-chip test system for high-speed (over 10 GHz) test. Including I/O circuits, the system as a whole consists of 1236 Josephson junctions. The chip was fabricated by using NEC's standard Nb process. We carried out an on-chip test and found correct operations up to 35 GHz.