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IEEE Transactions on Applied Superconductivity

SFQ standard cell-based circuit design of an internal link speeded-up Batcher-Banyan packet switch

Y. Kameda, Shinichi Yorozu, Shuichi Tahara

Published Mar 1, 2001• 13 citations

Abstract

We are developing a single-flux-quantum (SFQ) packet switch for over 1-Tb/s switching systems. Investigation of several switch topologies leads us to select the Batcher-Banyan packet switch because of its simplicity and regularity. The packet switch structure we propose consists of simple 2/spl times/2 unit switches each connected by speeded-up internal links. Numeric simulation showed that the speeded-up links greatly improved the throughput by resolving packet blocking, which is a major drawback of the Banyan switch. High throughput compatible to a crossbar switch was attained by using links whose speed was quadrupled. Moreover, the throughput did not decrease even though the number of input/output ports increased. Taking the speed of SFQ basic gates into account, the cycle time of the 2/spl times/2 unit switch reaches 25 ps, which is sufficient to achieve the 40-GHz operation. If unit switches are connected by quadrupled internal links, the Batcher-Banyan switch can accept the 10-Gb/s external input rate per channel. This indicates that the total throughput of a 128/spl times/128 switch exceeds 1 Tb/s. The unit switch was designed down to the SFQ gate level. To design a large SFQ circuit, we built several "standard" SFQ cells whose shape was square or rectangular with a unit width and height. Such shapes make it easier to place and connect a number of cells. We show some experimental results of testing SFQ standard cells and logic circuits.

DOI: 10.1109/77.919348

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We have carried out a paper feasibility study of the implementation of most common packet switching cores (crossbar, Batcher-banyan, time-division shared bus, and token ring) using the superconductor rapid single flux quantum (RSFQ) digital technology. According to our estimates, the best performance-to-complexity ratio may be obtained for the Batcher-banyan network. For example, a 128 by 128 switching core with self-routing (but without address translation, contention resolution, and broadcast features), consisting of about 180,000 Josephson junctions with the internal clock frequency of 60 GHz could handle a workload of 7.5 Tbps. This core could fit on a single 1 cm by 1 cm chip and dissipate as low as 45 mW. The estimated parameters are achievable using a simple 1.5-micrometer niobium- trilayer technology.

We evaluate the performance of a single flux quantum (SFQ) circuit and discuss its possible system-level application. First, we describe an optical-electrical-SFQ hybrid router system that is divided into three functions: an SFQ packet-routing function, a control function, and an optical transmission function. For the packet-switching core, we have developed a packet-switching architecture based on an internal speedup time-shifted Batcher Banyan approach. Our simulated results show that this architecture should provide good scalability and a low packet-loss rate. Additionally, we have fabricated an asynchronous pulse arbitration circuit. This circuit is a key component in our packet-switching system. The circuit synchronizes two asynchronous incoming signals without any global clock signals. It consists of a clock generator based on a ring oscillator and data latches. By measuring the average output voltage of the Josephson junction, we confirmed the output signal control by the clock at over 60 Gbps throughput.