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arXiv:2606.27508

I-QMapper: Error-Aware Layout Optimization and Device Diagnostics for NISQ Hardware

Milana Bazayeva, Kenneth Merz

quant-phSubmitted Jun 25, 2026• Announced Jun 29, 2026• 0 citations• Revised Aug 6, 2026 (v2)
v1 · Jun 25, 2026v2 · Aug 6, 2026
arXivHTMLPDF

Abstract

Achieving high-fidelity execution on noisy intermediate-scale quantum (NISQ) hardware requires careful selection of physical qubit layouts, as gate errors, readout errors, and coherence times vary across the device and drift over time. Currently, qubit mapping is performed either through manual inspection of device calibration data or through automated layout pipelines, neither of which provides integrated, interactive layout visualization combined with calibration analytics. In this work, we present the Interactive Quantum Mapper (I-QMapper), a Jupyter-based, open-source tool for noise-aware layout selection, visualization, and analysis on superconducting quantum hardware. I-QMapper offers two operating modes: a general-purpose mode for arbitrary circuits, and a dedicated mode for quantum-chemistry applications, specifically tailored to the Local Unitary Cluster Jastrow (LUCJ) ansatz. Within each mode, a Design panel supports interactive layout construction, while an Error panel provides calibration analytics through four temporal viewing modes (Live, Snapshot, Intraday, and Multi-day range) together with threshold filtering and delta-mode comparison for drift identification. Each layout receives a Layout-Quality Score (LQS) that aggregates the readout and two-qubit gate errors of the layout into a single quality value. Starting from the automatic LUCJ circuit-generation provided by IBM Quantum, we extend it to a multi-programming setting in which multiple circuits are mapped onto a single quantum processing unit (QPU). I-QMapper further supports side-by-side visualization of two quantum backends and layout comparison, and session export for experimental reproducibility. By combining interactive exploration with calibration analytics, I-QMapper aims to support both rapid layout prototyping and informed noise-aware experimental design on NISQ devices.

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Achieving high-fidelity execution on noisy intermediate-scale quantum (NISQ) hardware requires careful selection of physical qubit layouts, as gate errors, readout errors, and coherence times vary across the device and drift over time. Currently, qubit mapping is performed either through manual inspection of device calibration data or through automated layout pipelines, neither of which provides integrated, interactive layout visualization combined with calibration analytics. In this work, we present the Interactive Quantum Mapper (I-QMapper), a Jupyter-based, open-source tool for noise-aware layout selection, visualization, and analysis on superconducting quantum hardware. I-QMapper offers two operating modes: a general-purpose mode for arbitrary circuits, and a dedicated mode for quantum-chemistry applications, specifically tailored to the Local Unitary Cluster Jastrow (LUCJ) ansatz. Within each mode, a Design panel supports interactive layout construction, while an Error panel provides calibration analytics through four temporal viewing modes (Live, Snapshot, Intraday, and Multi-day range) together with threshold filtering and delta-mode comparison for drift identification. Each layout receives a Layout-Quality Score (LQS) that aggregates the readout and two-qubit gate errors of the layout into a single quality value. Starting from the automatic LUCJ circuit-generation provided by IBM Quantum, we extend it to a multi-programming setting in which multiple circuits are mapped onto a single quantum processing unit (QPU). I-QMapper further supports side-by-side visualization of two quantum backends and layout comparison, and session export for experimental reproducibility. By combining interactive exploration with calibration analytics, I-QMapper aims to support both rapid layout prototyping and informed noise-aware experimental design on NISQ devices.
Running quantum programs is fraught with challenges on on today's noisy intermediate scale quantum (NISQ) devices. Many of these challenges originate from the error characteristics that stem from rapid decoherence and noise during measurement, qubit connections, crosstalk, the qubits themselves, and transformations of qubit state via gates. Not only are qubits not “created equal”, but their noise level also changes over time. IBM is said to calibrate their quantum systems once per day and reports noise levels (errors) at the time of such calibration. This information is subsequently used to map circuits to higher quality qubits and connections up to the next calibration point. This work provides evidence that there is room for improvement over this daily calibration cycle. It contributes a technique to measure noise levels (errors) related to qubits immediately before executing one or more sensitive circuits and shows that just-in-time noise measurements can benefit late physical qubit mappings. With this just-in-time recalibrated transpilation, the fidelity of results is improved over IBM's default mappings, which only uses their daily calibrations. The framework assess two major sources of noise, namely readout errors (measurement errors) and two-qubit gate/connection errors. Experiments indicate that the accuracy of circuit results improves by 3-304% on average and up to 400% with on-the-fly circuit mappings based on error measurements just prior to application execution.
The rapid advancement of Noisy Intermediate-Scale Quantum (NISQ) devices has driven the need for efficient design automation tools that can translate complex engineering models into executable quantum circuits. This study explores the development of automated quantum circuit design frameworks focused on gate optimization and noise-aware compilation, enabling practical quantum computation for engineering applications such as optimization, simulation, and control systems. Traditional circuit design methods often fail to account for hardware constraints, decoherence, and gate infidelity, which significantly affect computational accuracy on NISQ devices. To address these challenges, this research introduces a hybrid automation approach combining quantum transpilation, variational circuit pruning, and error-aware synthesis algorithms to enhance circuit reliability and scalability. The framework integrates quantum-classical co-design principles to optimize both logical and physical circuit layers, leveraging hardware-specific calibration data to adapt compilation strategies dynamically. Through simulations and benchmark analysis, the proposed system demonstrates significant improvements in quantum resource utilization, error mitigation, and gate depth reduction compared to conventional compilation methods. This work underscores the growing importance of design automation in quantum engineering, where algorithmic efficiency must be harmonized with physical constraints to realize functional and scalable quantum workflows. By establishing a methodology for gate-level optimization and noise-adaptive design, the study contributes to bridging the gap between theoretical quantum algorithms and real-world engineering implementations within the NISQ computing era.
Reliably executing quantum algorithms on noisy intermediate-scale quantum (NISQ) devices is challenging, as they are severely constrained and prone to errors. Efficient quantum circuit compilation techniques are therefore crucial for overcoming their limitations and dealing with their high error rates. These techniques consider the quantum hardware restrictions, such as the limited qubit connectivity, and perform some transformations to the original circuit that can be executed on a given quantum processor. Certain compilation methods use error information based on calibration data to further improve the success probability or the fidelity of the circuit to be run. However, it is uncertain to what extent incorporating calibration information in the compilation process can enhance the circuit performance. For instance, considering the most recent error data provided by vendors after calibrating the processor might not be functional enough as quantum systems are subject to drift, making the latest calibration data obsolete within minutes. In this paper, we explore how different usage of calibration data impacts the circuit fidelity, by using several compilation techniques and quantum processors (IBM Perth and Brisbane). To this aim, we implemented a framework that incorporates some of the state-of-the-art noise-aware and non-noise-aware compilation techniques and allows the user to perform fair comparisons under similar processor conditions. Our experiments yield valuable insights into the effects of noise-aware methodologies and the employment of calibration data. The main finding is that pre-processing historical calibration data can improve fidelity when real-time calibration data is not available due to factors such as cloud service latency and waiting queues between compilation and execution on the quantum backend.
In order to enter the era of utility, noisy intermediate-scale quantum (NISQ) devices need to enable long-range entanglement of large qubit chains. However, due to the limited connectivity of superconducting NISQ devices, long-range entangling gates are realized in linear depth. Furthermore, a time-dependent degradation of the average CNOT gate fidelity is observed. Likely due to aging, this phenomenon further degrades entanglement capabilities. Our aim is to help in the current efforts to achieve utility and provide an opportunity to extend the utility lifespan of current devices -albeit by selecting fewer, high quality resources. To achieve this, we provide a method to transform user-provided CNOT and readout error requirements into a compliant partition onto which circuits can be executed. We demonstrate an improvement of up to 52 % in fidelity for a random CNOT chain of length 50 qubits and consistent improvements between 11.8% and 47.7% for chains between 10 and 40 in varying in increments of 10, respectively.
In order to enter the era of utility, noisy intermediate-scale quantum (NISQ) devices need to enable long-range entanglement of large qubit chains. However, due to the limited connectivity of superconducting NISQ devices, long-range entangling gates are realized in linear depth. Furthermore, a time-dependent degradation of the average CNOT gate fidelity is observed. Likely due to aging, this phenomenon further degrades entanglement capabilities. Our aim is to help in the current efforts to achieve utility and provide an opportunity to extend the utility lifespan of current devices --albeit by selecting fewer, high quality resources. To achieve this, we provide a method to transform user-provided CNOT and readout error requirements into a compliant partition onto which circuits can be executed. We demonstrate an improvement of up to 52% in fidelity for a random CNOT chain of length 50 qubits and consistent improvements between 11.8% and 47.7% for chains between 10 and 40 in varying in increments of 10, respectively.
The rapid evolution of Noisy Intermediate-Scale Quantum (NISQ) devices has intensified the need for robust compilation strategies capable of mitigating hardware-induced errors while maximizing computational efficiency. Quantum compilers play a pivotal role in translating high-level quantum algorithms into hardware-executable instructions, yet they face significant challenges related to qubit connectivity constraints, limited coherence times, and stochastic noise. This paper examines error-resilient quantum compiler design for efficient qubit mapping, gate optimization, and noise mitigation in NISQ-era devices, proposing a framework that integrates topology-aware mapping, adaptive gate synthesis, and probabilistic error suppression techniques. By synthesizing advances in quantum circuit optimization, hardware-aware scheduling, and hybrid classical–quantum error correction strategies, the study evaluates how compiler-level innovations can substantially enhance execution fidelity and resource efficiency. The findings suggest that intelligent compiler architectures are critical enablers of practical quantum advantage during the transitional NISQ phase, bridging theoretical algorithm design with real-world hardware constraints.