In order to enter the era of utility, noisy intermediate-scale quantum (NISQ) devices need to enable long-range entanglement of large qubit chains. However, due to the limited connectivity of superconducting NISQ devices, long-range entangling gates are realized in linear depth. Furthermore, a time-dependent degradation of the average CNOT gate fidelity is observed. Likely due to aging, this phenomenon further degrades entanglement capabilities. Our aim is to help in the current efforts to achieve utility and provide an opportunity to extend the utility lifespan of current devices --albeit by selecting fewer, high quality resources. To achieve this, we provide a method to transform user-provided CNOT and readout error requirements into a compliant partition onto which circuits can be executed. We demonstrate an improvement of up to 52% in fidelity for a random CNOT chain of length 50 qubits and consistent improvements between 11.8% and 47.7% for chains between 10 and 40 in varying in increments of 10, respectively.
In order to enter the era of utility, noisy intermediate-scale quantum (NISQ) devices need to enable long-range entanglement of large qubit chains. However, due to the limited connectivity of superconducting NISQ devices, long-range entangling gates are realized in linear depth. Furthermore, a time-dependent degradation of the average CNOT gate fidelity is observed. Likely due to aging, this phenomenon further degrades entanglement capabilities. Our aim is to help in the current efforts to achieve utility and provide an opportunity to extend the utility lifespan of current devices --albeit by selecting fewer, high quality resources. To achieve this, we provide a method to transform user-provided CNOT and readout error requirements into a compliant partition onto which circuits can be executed. We demonstrate an improvement of up to 52% in fidelity for a random CNOT chain of length 50 qubits and consistent improvements between 11.8% and 47.7% for chains between 10 and 40 in varying in increments of 10, respectively.
In order to enter the era of utility, noisy intermediate-scale quantum (NISQ) devices need to enable long-range entanglement of large qubit chains. However, due to the limited connectivity of superconducting NISQ devices, long-range entangling gates are realized in linear depth. Furthermore, a time-dependent degradation of the average CNOT gate fidelity is observed. Likely due to aging, this phenomenon further degrades entanglement capabilities. Our aim is to help in the current efforts to achieve utility and provide an opportunity to extend the utility lifespan of current devices -albeit by selecting fewer, high quality resources. To achieve this, we provide a method to transform user-provided CNOT and readout error requirements into a compliant partition onto which circuits can be executed. We demonstrate an improvement of up to 52 % in fidelity for a random CNOT chain of length 50 qubits and consistent improvements between 11.8% and 47.7% for chains between 10 and 40 in varying in increments of 10, respectively.
Noisy Intermediate-Scale Quantum (NISQ) devices are promising platforms for practical quantum computing, but their performance is significantly affected by limited qubit availability, gate errors, decoherence, circuit depth, and hardware-dependent noise. Conventional quantum circuits are generally designed and optimized before execution and may not respond effectively to changing hardware conditions during computation. This research proposes a Self-Adaptive Quantum Circuit framework that dynamically modifies quantum circuits according to the current computational resources and noise characteristics of NISQ devices. The proposed framework monitors parameters such as qubit fidelity, gate error rates, circuit depth, execution time, and resource availability, and automatically selects suitable circuit configurations to improve computational performance. Adaptive mechanisms can be employed to reduce unnecessary gates, optimize qubit utilization, and mitigate the impact of hardware noise while maintaining the required computational accuracy. The framework will be evaluated using simulation platforms and available NISQ quantum hardware, comparing adaptive circuits with conventional static circuits using metrics such as accuracy, fidelity, circuit depth, gate count, execution time, and error rate. The expected outcome is a resource-efficient and noise-aware quantum circuit optimization approach capable of improving the reliability and performance of quantum applications on near-term quantum hardware. The proposed research aims to contribute toward more practical, flexible, and hardware-aware quantum computing systems for NISQ-era applications. Keywords: NISQ Computing, Self-Adaptive Quantum Circuits, Quantum Circuit Optimization, Quantum Error Mitigation, Quantum Noise, Quantum Computing.
The current phase of quantum computing is in the Noisy Intermediate-Scale Quantum (NISQ) era. On NISQ devices, two-qubit gates such as CNOTs are much noisier than single-qubit gates, so it is essential to minimize their count. Quantum circuit synthesis is a process of decomposing an arbitrary unitary into a sequence of quantum gates, and can be used as an optimization tool to produce shorter circuits to improve overall circuit fidelity. However, the time-to-solution of synthesis grows exponentially with the number of qubits. As a result, synthesis is intractable for circuits on a large qubit scale.
In this paper, we propose a hierarchical, block-by-block optimization framework, QGo, for quantum circuit optimization. Our approach allows an exponential cost optimization to scale to large circuits. QGo uses a combination of partitioning and synthesis: 1) partition the circuit into a sequence of independent circuit blocks; 2) re-generate and optimize each block using quantum synthesis; and 3) re-compose the final circuit by stitching all the blocks together. We perform our analysis and show the fidelity improvements in three different regimes: small-size circuits on real devices, medium-size circuits on noise simulations, and large-size circuits on analytical models. Using a set of NISQ benchmarks, we show that QGo can reduce the number of CNOT gates by 29.9% on average and up to 50% when compared with industrial compilers such as t|ket>. When executed on the IBM Athens system, shorter depth leads to higher circuit fidelity. We also demonstrate the scalability of our QGo technique to optimize circuits of 60+ qubits. Our technique is the first demonstration of successfully employing and scaling synthesis in the compilation toolchain for large circuits. Overall, our approach is robust for direct incorporation in production compiler toolchains.
The rapid evolution of Noisy Intermediate-Scale Quantum (NISQ) devices has intensified the need for robust compilation strategies capable of mitigating hardware-induced errors while maximizing computational efficiency. Quantum compilers play a pivotal role in translating high-level quantum algorithms into hardware-executable instructions, yet they face significant challenges related to qubit connectivity constraints, limited coherence times, and stochastic noise. This paper examines error-resilient quantum compiler design for efficient qubit mapping, gate optimization, and noise mitigation in NISQ-era devices, proposing a framework that integrates topology-aware mapping, adaptive gate synthesis, and probabilistic error suppression techniques. By synthesizing advances in quantum circuit optimization, hardware-aware scheduling, and hybrid classical–quantum error correction strategies, the study evaluates how compiler-level innovations can substantially enhance execution fidelity and resource efficiency. The findings suggest that intelligent compiler architectures are critical enablers of practical quantum advantage during the transitional NISQ phase, bridging theoretical algorithm design with real-world hardware constraints.
In the current landscape of noisy intermediate-scale quantum (NISQ) computing, the inherent noise presents significant challenges to achieving high-fidelity long-range entanglement. Furthermore, this challenge is amplified by the limited connectivity of current superconducting devices, necessitating state permutations to establish long-distance entanglement. Traditionally, graph methods are used to satisfy the coupling constraints of a given architecture by routing states along the shortest undirected path between qubits. In this work, we introduce a gradient boosting machine learning model to predict the fidelity of alternative--potentially longer--routing paths to improve fidelity. This model was trained on 4050 random CNOT gates ranging in length from 2 to 100+ qubits. The experiments were all executed on ibm_quebec, a 127-qubit IBM Quantum System One. Through more than 200+ tests run on actual hardware, our model successfully identified higher fidelity paths in approximately 23% of cases.
Noisy intermediate-scale quantum (NISQ) devices impose dual challenges on quantum circuit execution: limited qubit connectivity requires extensive SWAP-gate routing, while time-dependent decoherence progressively degrades quantum information. Existing qubit-mapping algorithms optimize for hardware topology and static calibration metrics but systematically neglect transverse relaxation dynamics (T_2), creating a fundamental gap between compiler decisions and evolving noise characteristics. We present transverse relaxation time–aware qubit-mapping (TRAM), a coherence-guided compilation framework that elevates decoherence mitigation to a primary optimization objective. TRAM integrates calibration-informed community detection to construct noise-resilient qubit partitions, generates time-weighted initial mappings that anticipate coherence decay, and dynamically schedules SWAP operations to minimize cumulative error accumulation. Evaluated on Qiskit-based simulators with realistic noise models, TRAM outperforms SABRE by 3.29% in fidelity, reduces gate count by 11.47%, and shortens circuit depth by 12.29%, establishing coherence-aware optimization as essential for practical quantum compilation in the NISQ era.