Reliably executing quantum algorithms on noisy intermediate-scale quantum (NISQ) devices is challenging, as they are severely constrained and prone to errors. Efficient quantum circuit compilation techniques are therefore crucial for overcoming their limitations and dealing with their high error rates. These techniques consider the quantum hardware restrictions, such as the limited qubit connectivity, and perform some transformations to the original circuit that can be executed on a given quantum processor. Certain compilation methods use error information based on calibration data to further improve the success probability or the fidelity of the circuit to be run. However, it is uncertain to what extent incorporating calibration information in the compilation process can enhance the circuit performance. For instance, considering the most recent error data provided by vendors after calibrating the processor might not be functional enough as quantum systems are subject to drift, making the latest calibration data obsolete within minutes. In this paper, we explore how different usage of calibration data impacts the circuit fidelity, by using several compilation techniques and quantum processors (IBM Perth and Brisbane). To this aim, we implemented a framework that incorporates some of the state-of-the-art noise-aware and non-noise-aware compilation techniques and allows the user to perform fair comparisons under similar processor conditions. Our experiments yield valuable insights into the effects of noise-aware methodologies and the employment of calibration data. The main finding is that pre-processing historical calibration data can improve fidelity when real-time calibration data is not available due to factors such as cloud service latency and waiting queues between compilation and execution on the quantum backend.
Reliably executing quantum algorithms on noisy intermediate-scale quantum (NISQ) devices is challenging, as they are severely constrained and prone to errors. Efficient quantum circuit compilation techniques are therefore crucial for overcoming their limitations and dealing with their high error rates. These techniques consider the quantum hardware restrictions, such as the limited qubit connectivity, and perform some transformations to the original circuit that can be executed on a given quantum processor. Certain compilation methods use error information based on calibration data to further improve the success probability or the fidelity of the circuit to be run. However, it is uncertain to what extent incorporating calibration information in the compilation process can enhance the circuit performance. For instance, considering the most recent error data provided by vendors after calibrating the processor might not be functional enough as quantum systems are subject to drift, making the latest calibration data obsolete within minutes. In this paper, we explore how different usage of calibration data impacts the circuit fidelity, by using several compilation techniques and quantum processors (IBM Perth and Brisbane). To this aim, we implemented a framework that incorporates some of the state-of-the-art noise-aware and non-noise-aware compilation techniques and allows the user to perform fair comparisons under similar processor conditions. Our experiments yield valuable insights into the effects of noise-aware methodologies and the employment of calibration data. The main finding is that pre-processing historical calibration data can improve fidelity when real-time calibration data is not available due to factors such as cloud service latency and waiting queues between compilation and execution on the quantum backend.
Today’s Noisy Intermediate-Scale Quantum (NISQ) computers support only limited sets of available quantum gates and restricted connectivity. Therefore, quantum algorithms must be transpiled in order to become executable on a given NISQ computer; transpilation is a complex and computationally heavy process. Moreover, NISQ computers are affected by noise that changes over time, and periodic calibration provides relevant error rates that should be considered during transpilation. Variational algorithms, which form one main class of computations on NISQ platforms, produce a number of similar yet not identical quantum "ansatz" circuits. In this work, we present a transpilation methodology optimized for variational algorithms under potentially changing error rates. We divide transpilation into three steps: (1) noise-unaware and computationally heavy pre-transpilation; (2) fast noise-aware matching; and (3) fast decomposition followed by heuristic optimization. For a complete run of a variational algorithm under constant error rates, only step (3) needs to be executed for each new ansatz circuit. Step (2) is required only if the error rates reported by calibration have changed significantly since the beginning of the computation. The most expensive Step (1) is executed only once for the whole run. This distribution is helpful for incremental, calibration-aware transpilation when the variational algorithm adapts its own execution to changing error rates. Experimental results on IBM’s quantum computer show the low latency and robust results obtained by calibration-aware transpilation.
Multiple layers of the quantum system full-stack require data on temporal variations in error rates of physical elements. The absence of this information, especially when users access cloud-based quantum systems with waiting queues between compilation and execution, can lead to unreliable computations due to outdated calibration data. One example is the compilation process that impacts the success rate of quantum circuits. This paper proposes using five machine learning and time-series models to predict error rate variability for two-qubit gates based on calibration data. We compare model accuracy and complexity in terms of execution time. The predicted information is applied to a noise-aware compiler to evaluate the impact on success rate. Experimental results on a real superconducting quantum processor demonstrate accurate predictions of temporal error rate variability, achieving performance comparable to that of real calibration data, reducing the impact of queue waiting times that can reach up to two days.
The rapid advancement of Noisy Intermediate-Scale Quantum (NISQ) devices has driven the need for efficient design automation tools that can translate complex engineering models into executable quantum circuits. This study explores the development of automated quantum circuit design frameworks focused on gate optimization and noise-aware compilation, enabling practical quantum computation for engineering applications such as optimization, simulation, and control systems. Traditional circuit design methods often fail to account for hardware constraints, decoherence, and gate infidelity, which significantly affect computational accuracy on NISQ devices. To address these challenges, this research introduces a hybrid automation approach combining quantum transpilation, variational circuit pruning, and error-aware synthesis algorithms to enhance circuit reliability and scalability. The framework integrates quantum-classical co-design principles to optimize both logical and physical circuit layers, leveraging hardware-specific calibration data to adapt compilation strategies dynamically. Through simulations and benchmark analysis, the proposed system demonstrates significant improvements in quantum resource utilization, error mitigation, and gate depth reduction compared to conventional compilation methods. This work underscores the growing importance of design automation in quantum engineering, where algorithmic efficiency must be harmonized with physical constraints to realize functional and scalable quantum workflows. By establishing a methodology for gate-level optimization and noise-adaptive design, the study contributes to bridging the gap between theoretical quantum algorithms and real-world engineering implementations within the NISQ computing era.
Abstract Quantum computing has recently emerged as a novel paradigm for solving problems otherwise intractable on classical computers, yet the practical progress of quantum computers is severely impacted by noise, decoherence, and imperfect gate operations in Noisy Intermediate-Scale Quantum (NISQ) devices. Specific to IBM Quantum hardware, imperfections due to readout error, gate errors, and device drift, which depends on time, resolves limits for the accuracy of outputs from our algorithms. The mitigation strategies currently used, for example, Measurement Error Mitigation (MEM), Zero Noise Extrapolation (ZNE), and Clifford Data Regression (CDR), offer improvement over raw, unmitigated outputs, but they are static and not dynamic; the reduction of noise in within an NISQ device is temporal and can vary in patterns that are non-zero. In addition to this, using the conventional methods provides inconsistent and suboptimal results.This study will provide enhanced reliability with respect to performing quantum computation on IBM Quantum hardware with a unique mitigation framework that is adaptive and computationally efficient for a high-fidelity output. The problem taken on here is the failure of existing error mitigation strategies to provide adaptive noise compensation, as they assume a statically-distributed error, despite the performance-related characteristics already being documented in regards to calibration drift and variation over time.To achieve this, we propose a Hybrid Adaptive Error Mitigation (HAEM) approach that includes baseline measurement error mitigation and an additional correction layer that utilizes realtime calibration information, along with lightweight machine learning models. The approach can be broken down into three steps: (i) perform standard measurement error mitigation to reduce classical readout noise, (ii) execute compact calibration circuits, such as Bell states, GHZ states and Clifford benchmarks to capture then current error profile of the device, and (iii) use a lightweight machine learning model (having been trained on historical and newest calibration data) to dynamically change the mitigation weights applied for the target quantum algorithm. All implementation is done using Qiskit Runtime to ensure low-latency execution, and we completed experiments on both Qiskit Aer noisy simulators and IBM Quantum devices.Initial results suggest HAEM improved the outputs of quantum algorithms' fidelity compared to the unmitigated runs and the baseline measurement error mitigation (MEM) runs. On the noisy simulators, HAEM increased fidelity from a raw performance of 0.65 to 0.87, nearly a 34% improvement. In fairer hardware-like scenarios, fidelity-on-average was persistently 12% better than MEM, with nearly equal time duration for the additional adaptive measurements. The adaptive aspect of HAEM consistently supported subsequent calibration cycles of the device and was effective to continue providing fidelity improvements despite the static mitigation performance degrading.To sum up, the proposed HAEM framework is a modern and viable alternative for error mitigation which brings together the benefits of baseline approaches with corrections that are driven by fixed-function error-corrective, adaptive learning. As both learning-based and standard baseline approaches can only achieve fixed levels of performance, HAEM, through its use of noise mitigation both at execution time and through correlating it with standard data, provides a route towards reliable quantum computations on current IBM hardware. HAEM also presents a contribution to the NISQ error-resilient landscape, and however it is intended that it will continue to improve future applications of hybrid workflows of quantum and classical computation where error mitigation and resilience is important.
Running quantum programs is fraught with challenges on on today's noisy intermediate scale quantum (NISQ) devices. Many of these challenges originate from the error characteristics that stem from rapid decoherence and noise during measurement, qubit connections, crosstalk, the qubits themselves, and transformations of qubit state via gates. Not only are qubits not “created equal”, but their noise level also changes over time. IBM is said to calibrate their quantum systems once per day and reports noise levels (errors) at the time of such calibration. This information is subsequently used to map circuits to higher quality qubits and connections up to the next calibration point. This work provides evidence that there is room for improvement over this daily calibration cycle. It contributes a technique to measure noise levels (errors) related to qubits immediately before executing one or more sensitive circuits and shows that just-in-time noise measurements can benefit late physical qubit mappings. With this just-in-time recalibrated transpilation, the fidelity of results is improved over IBM's default mappings, which only uses their daily calibrations. The framework assess two major sources of noise, namely readout errors (measurement errors) and two-qubit gate/connection errors. Experiments indicate that the accuracy of circuit results improves by 3-304% on average and up to 400% with on-the-fly circuit mappings based on error measurements just prior to application execution.
The rapid evolution of Noisy Intermediate-Scale Quantum (NISQ) devices has intensified the need for robust compilation strategies capable of mitigating hardware-induced errors while maximizing computational efficiency. Quantum compilers play a pivotal role in translating high-level quantum algorithms into hardware-executable instructions, yet they face significant challenges related to qubit connectivity constraints, limited coherence times, and stochastic noise. This paper examines error-resilient quantum compiler design for efficient qubit mapping, gate optimization, and noise mitigation in NISQ-era devices, proposing a framework that integrates topology-aware mapping, adaptive gate synthesis, and probabilistic error suppression techniques. By synthesizing advances in quantum circuit optimization, hardware-aware scheduling, and hybrid classical–quantum error correction strategies, the study evaluates how compiler-level innovations can substantially enhance execution fidelity and resource efficiency. The findings suggest that intelligent compiler architectures are critical enablers of practical quantum advantage during the transitional NISQ phase, bridging theoretical algorithm design with real-world hardware constraints.