In this study, we propose an efficient quantum multiplication approach based on a QFT-assisted parallelized addition scheme. The multiplication stage is implemented using a structure composed entirely of Toffoli gates, which generate partial products. In the second stage, these partial results are accumulated using a QFT-based adder. Unlike conventional QFT-based arithmetic circuits, the proposed design eliminates the repeated application of QFT and inverse QFT (IQFT) operations during intermediate summation processes. This leads to a significant reduction in the total gate count and circuit complexity, enabling a more resource-efficient implementation. To demonstrate the feasibility of the proposed approach, a quantum circuit that performs the multiplication of two 3-bit numbers is designed. The circuit is tested and validated using IBM quantum simulators. The results indicate that the proposed method provides a more efficient alternative to traditional quantum multiplication techniques in terms of gate cost and circuit depth.
In this study, we propose an efficient quantum multiplication approach based on a QFT-assisted parallelized addition scheme. The multiplication stage is implemented using a structure composed entirely of Toffoli gates, which generate partial products. In the second stage, these partial results are accumulated using a QFT-based adder. Unlike conventional QFT-based arithmetic circuits, the proposed design eliminates the repeated application of QFT and inverse QFT (IQFT) operations during intermediate summation processes. This leads to a significant reduction in the total gate count and circuit complexity, enabling a more resource-efficient implementation. To demonstrate the feasibility of the proposed approach, a quantum circuit that performs the multiplication of two 3-bit numbers is designed. The circuit is tested and validated using IBM quantum simulators. The results indicate that the proposed method provides a more efficient alternative to traditional quantum multiplication techniques in terms of gate cost and circuit depth.
Quantum squaring circuits have been used as helpful arithmetic modules in various quantum algorithms for calculating series expansions or distances of vectors, etc. Quantum multipliers can replace quantum squaring circuits, but squaring with quantum multipliers is inefficient because it involves using quantum gates for unnecessary bitwise multiplication. In this paper, we propose a depth-optimized quantum circuit dedicated to squaring by eliminating these unnecessary quantum gates and implementing quantum gates in parallel. We also discuss the optimal distribution of the partial products to reduce further the gate cost of the quantum adder used for the sum of the partial products. The proposed partial product distribution method lowers the quantum adder’s number of gates and depth by half. Our quantum squaring circuit is the most efficient, with an average improvement of 68% and 79.7% in T-count and T-depth, respectively, compared to existing quantum squaring circuits. Despite the increased qubit counts caused by the depth optimization, we demonstrate that the proposed circuit has the smallest KQT .
Quantum computing (Q-computing) is a revolutionary technology that applies quantum mechanics (QM) to implement calculations significantly quicker than traditional computers. Q-computing employs Q-bits (qubits) rather than classical bits, which can take on a superposition state, making it possible to represent both 0 and 1 at once. This distinctive property allows qubits to perform multiple calculations simultaneously, making Q computers exponentially more powerful as more qubits are added, compared to the linear scaling of classical computers. However, challenges such as qubit instability and error rates remain significant obstacles to fully realizing this potential. A vital aspect of this technology is the development of Q arithmetic circuits, which act as the foundational blocks for efficiently executing Q algorithms. Q half-adder and full-adder circuits are integral to performing fundamental arithmetic operations within Q computers. In contrast to classical adders, Q adders rely on Q gates such as Controlled NOT (CNOT) and Toffoli gates. These gates exploit Q phenomena like entanglement and superposition, allowing for more efficient computations. The Q half-adder consists of two qubits and adds two single bits, producing a carry and sum output. It utilizes the CNOT gate to compute the sum and the Toffoli gate (controlled-controlled-NOT [CCNOT]) to compute the carry. The Q full-adder builds on this, adding three qubits to produce a sum and a carry output, further increasing computational capacity. Through the entanglement of qubits, these circuits allow for more parallelism and speed compared to classical adders. Q carry-look-ahead adders (QCLAs) and Q ripple-carry adders (QRCAs) are used to perform more complex arithmetic operations based on these half-adder and full-adder structures. Q arithmetic circuits have broad applications, boosting secure key generation in cryptography, speeding up matrix operations for faster model training in machine learning, and enabling more precise, efficient image transformations in Q image processing, benefiting fields like medical imaging and computer vision.
In this research, we create a scalable version of the quantum Fourier transform-based arithmetic circuit to perform addition and subtraction operations on N n-bit unsigned integers encoded in quantum registers, and it is compatible with d-level quantum sources, called qudits. We present qubit- and ququart-based multi-input QFT adders, and we compare and discuss potential benefits such as circuit simplicity and noise sensitivity. The results show that a ququart-based system significantly reduces gate count and improves computational efficiency compared to qubit-based systems. Overall, the findings presented in this study represent a promising step forward in the development of efficient quantum arithmetic circuits, particularly for multi-input operations, with clear advantages for ququart-based systems in reducing gate count, decoherence, and circuit complexity.
Addition is a key arithmetic operation in computing, as the rest of arithmetic operations are somewhat based on it. Focusing on quantum computing, addition can be implemented in different ways, such as adapting the ripple-carry adder from classical computing, or using a QFT-based adder, which is more efficient than the former. However, a Toffoli-based adder is in fact an alternative way to optimize QFT-based adders by merging rotation gates into a string of controlled-NOT and Toffoli gates with different control qubits. In this paper, the basics of matrix analysis of quantum circuits are described, which in turn are used to perform a matrix analysis of Toffoli adder circuits.
Quantum computing is a transformative technology providing exponential speedup over classical computing for specific computational problems. At the foundation of computing lies arithmetic, with addition as a fundamental operation for subtraction, multiplication, division, and other operations. In this paper, we evaluate the performance of quantum arithmetic circuits – including half adders, full adders, Toffoli-based adders, Quantum Fourier Transform (QFT)-based adders, and quantum comparators – on IBM’s Eagle Processor, a 127-qubit superconducting Quantum Processing Unit (QPU) accessible through the IBM Quantum cloud platform. These circuits are implemented using IBM Qiskit and tested on both ideal and noisy simulators to validate their functionality before execution on quantum hardware. Experimental results show that the probabilities of accurate computations are notably low, even for smaller input sizes, due to hardware imperfections such as shorter qubit coherence times and limited qubit stability. A comparative analysis of Toffoli-based and QFT-based adders demonstrates that Toffoli-based adders have higher accuracy, making them more suitable for precise quantum arithmetic operations. These findings highlight the significant impact of quantum hardware imperfections on the reliability of arithmetic operations.
This paper presents the design, optimization, and simulation of arithmetic circuits using reversible logic for quantum computing applications. The motivation behind this work is to achieve resource-efficient computation through reduced quantum cost, minimized garbage outputs, and lower ancilla requirements. The methodology involves implementing Half Adders, Full Adders, Multiplexers, and Ripple Carry Adders (RCAs) using Toffoli and Peres gates. The proposed 8-bit RCA achieves a quantum cost of 58 using 24 qubits, 8 garbage outputs, and 6 ancilla inputs—showing a significant improvement over conventional Toffoli-based designs that require higher quantum cost and resources. Simulations were conducted on IBM Qiskit and Google Colab using the Qiskit SDK to validate circuit correctness and scalability. The obtained results demonstrate superior resource efficiency and confirm the feasibility of reversible-logic-based quantum arithmetic as a foundation for scalable quantum arithmetic logic units (ALUs) and processors.