Addition is a key arithmetic operation in computing, as the rest of arithmetic operations are somewhat based on it. Focusing on quantum computing, addition can be implemented in different ways, such as adapting the ripple-carry adder from classical computing, or using a QFT-based adder, which is more efficient than the former. However, a Toffoli-based adder is in fact an alternative way to optimize QFT-based adders by merging rotation gates into a string of controlled-NOT and Toffoli gates with different control qubits. In this paper, the basics of matrix analysis of quantum circuits are described, which in turn are used to perform a matrix analysis of Toffoli adder circuits.
Addition is a key arithmetic operation in computing, as the rest of arithmetic operations are somewhat based on it. Focusing on quantum computing, addition can be implemented in different ways, such as adapting the ripple-carry adder from classical computing, or using a QFT-based adder, which is more efficient than the former. However, a Toffoli-based adder is in fact an alternative way to optimize QFT-based adders by merging rotation gates into a string of controlled-NOT and Toffoli gates with different control qubits. In this paper, the basics of matrix analysis of quantum circuits are described, which in turn are used to perform a matrix analysis of Toffoli adder circuits.
Quantum computing (Q-computing) is a revolutionary technology that applies quantum mechanics (QM) to implement calculations significantly quicker than traditional computers. Q-computing employs Q-bits (qubits) rather than classical bits, which can take on a superposition state, making it possible to represent both 0 and 1 at once. This distinctive property allows qubits to perform multiple calculations simultaneously, making Q computers exponentially more powerful as more qubits are added, compared to the linear scaling of classical computers. However, challenges such as qubit instability and error rates remain significant obstacles to fully realizing this potential. A vital aspect of this technology is the development of Q arithmetic circuits, which act as the foundational blocks for efficiently executing Q algorithms. Q half-adder and full-adder circuits are integral to performing fundamental arithmetic operations within Q computers. In contrast to classical adders, Q adders rely on Q gates such as Controlled NOT (CNOT) and Toffoli gates. These gates exploit Q phenomena like entanglement and superposition, allowing for more efficient computations. The Q half-adder consists of two qubits and adds two single bits, producing a carry and sum output. It utilizes the CNOT gate to compute the sum and the Toffoli gate (controlled-controlled-NOT [CCNOT]) to compute the carry. The Q full-adder builds on this, adding three qubits to produce a sum and a carry output, further increasing computational capacity. Through the entanglement of qubits, these circuits allow for more parallelism and speed compared to classical adders. Q carry-look-ahead adders (QCLAs) and Q ripple-carry adders (QRCAs) are used to perform more complex arithmetic operations based on these half-adder and full-adder structures. Q arithmetic circuits have broad applications, boosting secure key generation in cryptography, speeding up matrix operations for faster model training in machine learning, and enabling more precise, efficient image transformations in Q image processing, benefiting fields like medical imaging and computer vision.
Quantum addition circuits are considered being of two types: (1) Toffoli-adder circuits which use only classical reversible gates (controlled-not and Toffoli), and (2) QFT-adder circuits based on the quantum Fourier transformation. We present a systematic translation of the QFT addition circuit into a Toffoli-based adder. This result shows that QFT addition has fundamentally the same fault-tolerance cost (e.g., T count) as the most cost-efficient Toffoli adder: instead of using approximate decompositions of the gates from the QFT circuit, it is more efficient to merge gates. In order to achieve this, we formulated circuit identities for multicontrolled gates and apply the identities algorithmically. The employed techniques can be used to automate quantum circuit optimization heuristics.
A quantum gate is the quantum analog of the classical logic gate of digital computers. It is a basic structural unit of a quantum circuit which operates on a small number of qubits to deliver a predefined output. A quantum circuit is a graphical representation of the sequence of the quantum gates used and the measurements performed in a quantum computation. Various quantum logic gates, namely, the Hadamard, T phase, NOT, Pauli-X, controlled NOT (CNOT), controlled-Z, SWAP and controlled phase gates as well as higher-level Toffoli and Fredkin gates are described. Conventions of reading quantum circuit diagrams are explained. Operation of a quantum full adder consisting of registers and gates is discussed, elaborating the role of the NOT gate, the sum calculation with CNOTgates and the carry C-out calculation with Toffoli gates. A primary tool used for performing arithmetic operations on a quantum computer is the quantum Fourier transform (QFT). The QFT adder and multiplier circuits are presented.
The basic components of both quantum and quantum-inspired arithmetic systems are quantum adders. Traditional direct quantum adders like the Vedral and Cuccaro ripple-carry adders provide accurate computation but have higher circuit depth, longer propagation delay and complexity of hardware implementation based upon extensive usage of Toffoli gates. This article brings about a comparison analysis of the current quantum adder designs, and it suggests an Approximate Toffoli Adder in order to enhance performance and hardware efficiency. The suggested design is designed with the help of Verilog HDL and run with Xilinx Vivado 2025.2. As can be seen from experimental results, the Vedral and Cuccaro adders have a critical path delay of 7.999 ns and 7.979 ns, respectively, and the total on-chip power consumption of 2.945 W. Conversely, the Approximate Toffoli Adder proposed has a low critical path delay of 7.261 ns, lower power consumption of 2.442 W and less hardware consumption with 18 logic cells than the current designs with 20 logic cells. Analysis of errors ensures that there is a minimal difference in the accuracy of the output. It is proven that approximate arithmetic offers a successful trade-off between precision, speed, and power efficiency to use in quantum-inspired computing.
In this study, we propose an efficient quantum multiplication approach based on a QFT-assisted parallelized addition scheme. The multiplication stage is implemented using a structure composed entirely of Toffoli gates, which generate partial products. In the second stage, these partial results are accumulated using a QFT-based adder. Unlike conventional QFT-based arithmetic circuits, the proposed design eliminates the repeated application of QFT and inverse QFT (IQFT) operations during intermediate summation processes. This leads to a significant reduction in the total gate count and circuit complexity, enabling a more resource-efficient implementation. To demonstrate the feasibility of the proposed approach, a quantum circuit that performs the multiplication of two 3-bit numbers is designed. The circuit is tested and validated using IBM quantum simulators. The results indicate that the proposed method provides a more efficient alternative to traditional quantum multiplication techniques in terms of gate cost and circuit depth.
This paper presents the design, optimization, and simulation of arithmetic circuits using reversible logic for quantum computing applications. The motivation behind this work is to achieve resource-efficient computation through reduced quantum cost, minimized garbage outputs, and lower ancilla requirements. The methodology involves implementing Half Adders, Full Adders, Multiplexers, and Ripple Carry Adders (RCAs) using Toffoli and Peres gates. The proposed 8-bit RCA achieves a quantum cost of 58 using 24 qubits, 8 garbage outputs, and 6 ancilla inputs—showing a significant improvement over conventional Toffoli-based designs that require higher quantum cost and resources. Simulations were conducted on IBM Qiskit and Google Colab using the Qiskit SDK to validate circuit correctness and scalability. The obtained results demonstrate superior resource efficiency and confirm the feasibility of reversible-logic-based quantum arithmetic as a foundation for scalable quantum arithmetic logic units (ALUs) and processors.