The basic components of both quantum and quantum-inspired arithmetic systems are quantum adders. Traditional direct quantum adders like the Vedral and Cuccaro ripple-carry adders provide accurate computation but have higher circuit depth, longer propagation delay and complexity of hardware implementation based upon extensive usage of Toffoli gates. This article brings about a comparison analysis of the current quantum adder designs, and it suggests an Approximate Toffoli Adder in order to enhance performance and hardware efficiency. The suggested design is designed with the help of Verilog HDL and run with Xilinx Vivado 2025.2. As can be seen from experimental results, the Vedral and Cuccaro adders have a critical path delay of 7.999 ns and 7.979 ns, respectively, and the total on-chip power consumption of 2.945 W. Conversely, the Approximate Toffoli Adder proposed has a low critical path delay of 7.261 ns, lower power consumption of 2.442 W and less hardware consumption with 18 logic cells than the current designs with 20 logic cells. Analysis of errors ensures that there is a minimal difference in the accuracy of the output. It is proven that approximate arithmetic offers a successful trade-off between precision, speed, and power efficiency to use in quantum-inspired computing.
The basic components of both quantum and quantum-inspired arithmetic systems are quantum adders. Traditional direct quantum adders like the Vedral and Cuccaro ripple-carry adders provide accurate computation but have higher circuit depth, longer propagation delay and complexity of hardware implementation based upon extensive usage of Toffoli gates. This article brings about a comparison analysis of the current quantum adder designs, and it suggests an Approximate Toffoli Adder in order to enhance performance and hardware efficiency. The suggested design is designed with the help of Verilog HDL and run with Xilinx Vivado 2025.2. As can be seen from experimental results, the Vedral and Cuccaro adders have a critical path delay of 7.999 ns and 7.979 ns, respectively, and the total on-chip power consumption of 2.945 W. Conversely, the Approximate Toffoli Adder proposed has a low critical path delay of 7.261 ns, lower power consumption of 2.442 W and less hardware consumption with 18 logic cells than the current designs with 20 logic cells. Analysis of errors ensures that there is a minimal difference in the accuracy of the output. It is proven that approximate arithmetic offers a successful trade-off between precision, speed, and power efficiency to use in quantum-inspired computing.
Approximate quantum adders are gaining traction in NISQ-era computing for their potential to reduce quantum resource usage while preserving computational accuracy. In this work, we evaluate two 8-qubit hybrid approximate quantum adders that combine a 2-qubit approximate block, either a pass-through Copy Adder or a CNOT-based design, with a 6-qubit Cuccaro ripple-carry adder. Simulations are conducted using IBM's Qiskit framework under realistic noise models, including bit-flip, depolarizing, and thermal noise. Compared to the exact 8-bit Cuccaro adder, our designs reduce quantum cost and circuit depth by over 20 percent and achieve up to 79.3 percent higher output probability under noisy conditions. These results highlight the robustness and efficiency of approximate logic in noisy quantum environments and confirm its practicality for near-term quantum hardware.
This paper presents the design, optimization, and simulation of arithmetic circuits using reversible logic for quantum computing applications. The motivation behind this work is to achieve resource-efficient computation through reduced quantum cost, minimized garbage outputs, and lower ancilla requirements. The methodology involves implementing Half Adders, Full Adders, Multiplexers, and Ripple Carry Adders (RCAs) using Toffoli and Peres gates. The proposed 8-bit RCA achieves a quantum cost of 58 using 24 qubits, 8 garbage outputs, and 6 ancilla inputs—showing a significant improvement over conventional Toffoli-based designs that require higher quantum cost and resources. Simulations were conducted on IBM Qiskit and Google Colab using the Qiskit SDK to validate circuit correctness and scalability. The obtained results demonstrate superior resource efficiency and confirm the feasibility of reversible-logic-based quantum arithmetic as a foundation for scalable quantum arithmetic logic units (ALUs) and processors.
Quantum computing (Q-computing) is a revolutionary technology that applies quantum mechanics (QM) to implement calculations significantly quicker than traditional computers. Q-computing employs Q-bits (qubits) rather than classical bits, which can take on a superposition state, making it possible to represent both 0 and 1 at once. This distinctive property allows qubits to perform multiple calculations simultaneously, making Q computers exponentially more powerful as more qubits are added, compared to the linear scaling of classical computers. However, challenges such as qubit instability and error rates remain significant obstacles to fully realizing this potential. A vital aspect of this technology is the development of Q arithmetic circuits, which act as the foundational blocks for efficiently executing Q algorithms. Q half-adder and full-adder circuits are integral to performing fundamental arithmetic operations within Q computers. In contrast to classical adders, Q adders rely on Q gates such as Controlled NOT (CNOT) and Toffoli gates. These gates exploit Q phenomena like entanglement and superposition, allowing for more efficient computations. The Q half-adder consists of two qubits and adds two single bits, producing a carry and sum output. It utilizes the CNOT gate to compute the sum and the Toffoli gate (controlled-controlled-NOT [CCNOT]) to compute the carry. The Q full-adder builds on this, adding three qubits to produce a sum and a carry output, further increasing computational capacity. Through the entanglement of qubits, these circuits allow for more parallelism and speed compared to classical adders. Q carry-look-ahead adders (QCLAs) and Q ripple-carry adders (QRCAs) are used to perform more complex arithmetic operations based on these half-adder and full-adder structures. Q arithmetic circuits have broad applications, boosting secure key generation in cryptography, speeding up matrix operations for faster model training in machine learning, and enabling more precise, efficient image transformations in Q image processing, benefiting fields like medical imaging and computer vision.
In the context of modern Very Large-Scale Integration (VLSI) technology, information loss has been a major concern. Logic gates (LG) such as AND, OR, and NOT have been found to result in information loss during their operations. To address this issue, reversible LGs have been created. The development and implementation of a high-speed, efficient full adder circuit employing reversible LGs like Feynman, Toffoli, and Peres gates. The design aims to improve computational and thermal efficiencies. The circuit refarding quantum costs (QC), garbage outputs, and ancillary inputs. The implemented the suggested design in Verilog and verified the entire adder's functionality and efficiency through simulations using the Xilinx Vivado and Xilinx ISE tools. The circuit has a quantum cost of 10 with two outputs of useless and one auxiliary input, according to the researchers, highlighting its opportunities for usage in quantum computing applications andlow-power (dec 84%), high-performance computing systems.
A reconfigurable 16-bit adder utilizing reversible logic is introduced to enhance both energy efficiency and computational performance. The design integrates Toffoli, Peres, and Haghparast–Navi Gate (HNG) to construct optimized full adder units with lower quantum cost, reduced garbage outputs, and minimal constant inputs. A reversible multiplexer is employed to enable seamless switching between Ripple Carry Adder (RCA) and Carry Lookahead Adder (CLA) configurations. While RCA mode supports power-efficient operation, CLA mode enables faster computation, allowing the circuit to adapt to different processing requirements. Performance evaluation is carried out considering propagation delay, power consumption and hardware utilization. The analysis indicates enhanced efficiency over existing reversible adder designs. Due to its adaptable structure and scalable nature, the architecture is appropriate for reversible computing, quantum systems, and low-power VLSI applications.
Addition is a key arithmetic operation in computing, as the rest of arithmetic operations are somewhat based on it. Focusing on quantum computing, addition can be implemented in different ways, such as adapting the ripple-carry adder from classical computing, or using a QFT-based adder, which is more efficient than the former. However, a Toffoli-based adder is in fact an alternative way to optimize QFT-based adders by merging rotation gates into a string of controlled-NOT and Toffoli gates with different control qubits. In this paper, the basics of matrix analysis of quantum circuits are described, which in turn are used to perform a matrix analysis of Toffoli adder circuits.