A reconfigurable 16-bit adder utilizing reversible logic is introduced to enhance both energy efficiency and computational performance. The design integrates Toffoli, Peres, and Haghparast–Navi Gate (HNG) to construct optimized full adder units with lower quantum cost, reduced garbage outputs, and minimal constant inputs. A reversible multiplexer is employed to enable seamless switching between Ripple Carry Adder (RCA) and Carry Lookahead Adder (CLA) configurations. While RCA mode supports power-efficient operation, CLA mode enables faster computation, allowing the circuit to adapt to different processing requirements. Performance evaluation is carried out considering propagation delay, power consumption and hardware utilization. The analysis indicates enhanced efficiency over existing reversible adder designs. Due to its adaptable structure and scalable nature, the architecture is appropriate for reversible computing, quantum systems, and low-power VLSI applications.
A reconfigurable 16-bit adder utilizing reversible logic is introduced to enhance both energy efficiency and computational performance. The design integrates Toffoli, Peres, and Haghparast–Navi Gate (HNG) to construct optimized full adder units with lower quantum cost, reduced garbage outputs, and minimal constant inputs. A reversible multiplexer is employed to enable seamless switching between Ripple Carry Adder (RCA) and Carry Lookahead Adder (CLA) configurations. While RCA mode supports power-efficient operation, CLA mode enables faster computation, allowing the circuit to adapt to different processing requirements. Performance evaluation is carried out considering propagation delay, power consumption and hardware utilization. The analysis indicates enhanced efficiency over existing reversible adder designs. Due to its adaptable structure and scalable nature, the architecture is appropriate for reversible computing, quantum systems, and low-power VLSI applications.
This paper presents the design, optimization, and simulation of arithmetic circuits using reversible logic for quantum computing applications. The motivation behind this work is to achieve resource-efficient computation through reduced quantum cost, minimized garbage outputs, and lower ancilla requirements. The methodology involves implementing Half Adders, Full Adders, Multiplexers, and Ripple Carry Adders (RCAs) using Toffoli and Peres gates. The proposed 8-bit RCA achieves a quantum cost of 58 using 24 qubits, 8 garbage outputs, and 6 ancilla inputs—showing a significant improvement over conventional Toffoli-based designs that require higher quantum cost and resources. Simulations were conducted on IBM Qiskit and Google Colab using the Qiskit SDK to validate circuit correctness and scalability. The obtained results demonstrate superior resource efficiency and confirm the feasibility of reversible-logic-based quantum arithmetic as a foundation for scalable quantum arithmetic logic units (ALUs) and processors.
This paper presents the design and implementation of a reversible 4×4 enhanced multiplier using quantum logic principles. The proposed architecture employs Toffoli and Peres gates to realize reversible AND gates and full adders, respectively, ensuring minimal energy dissipation in accordance with Landauer's principle. A layered structure is introduced to improve computation speed and modular scalability while maintaining reversibility. The design effectively reduces garbage outputs and constant inputs, which are critical performance parameters in reversible computing. Simulation results verify the functional correctness of the multiplier and demonstrate its potential for application in quantum computing, low-power VLSI design, and nanotechnology-based systems. The modular nature of the architecture also supports scalability for higher-order multipliers with minimal design overhead.
In modern Very-Large-Scale Integration (VLSI) technology, managing information loss is a critical challenge. Conventional logic gates, such as AND, OR, and NOT, are prone to data loss during operations, reducing their efficiency for sophisticated applications. Reversible logic gates, which have an equal number of inputs and outputs, offer a solution by preserving data integrity. This paper presents the design and FPGA implementation of an efficient and high-speed full adder circuit utilizing reversible logic gates, namely Feynman, Toffoli, and Peres gates. The design focuses on improving computational efficiency and thermal performance. An analysis of the circuit's quantum cost, garbage outputs, and ancillary inputs reveals its advantages over traditional designs. Proposed design has been realized using Verilog and Synthesize and simulations performed using Xilinx Vivado and Xilinx ISE tools, confirms the functionality and efficiency of the proposed full adder. FPGA implementation of the design has been done using NEXYS A7 (Artix 7 series). The results show that the circuit has a quantum cost of 10, with two garbage outputs and one ancillary input, underscoring its potential for use in low-power, high-performance computing systems and quantum computing applications.
Programmable reversible logic is emerging as a prospective logic design style for implementation in modern nanotechnology and quantum computing with minimal impact on circuit heat generation. Recent advances in reversible logic using and quantum computer algorithms allow for improved computer architecture and arithmetic logic unit designs. In this paper, a 2*2 Swap gate which is a reduced implementation in terms of quantum cost and delay to the previous Swap gate is presented. Next, a novel 3*3 programmable UPG gate capable of calculating the fundamental logic calculations is presented and verified, and its advantages over the Toffoli and Peres gates are discussed. The UPG is then implemented in a reduced design for calculating n-bit AND, nbit OR and n-bit ZERO calculations. Then, two 3*3 RMUX gates capable of multiplexing two input values with reduced quantum cost and delay compared to the previously existing Fredkin gate is presented and verified. Next, 4*4 reversible gate is presented and verified which is capable of producing the calculations necessary for two-bit comparisons. The UPG and RC are implemented in the design of novel sequential and tree-based comparators. Then, two novel 4*4 reversible logic gates (MRG and PAOG) are proposed with minimal delay, and may be configured to produce a variety of logical calculations on fixed output lines based on programmable select input lines. A 5*5 structure (MG) is proposed that extends the capabilities of both the MRG and PAOG. The comparator designs are verified and its advantages to previous designs are discussed. Then, reversible implementations of ripple-carry, carry-select and Kogge-Stone carry look-ahead adders are analyzed and compared. Next, implementations of the Kogge-Stone adder with sparsity-4, 8 and 16 were designed, verified and compared. The enhanced sparsity-4 Kogge-Stone adder with ripple-carry adders was selected as the best design, and its implemented in the design of a 32-bit arithmetic logic unit is demonstrated. The proposed ALU design is verified and its advantages over the only existing ALU design are quantitatively analyzed.
Efficient arithmetic operations are a prerequisite for practical quantum computing. Optimization efforts focus on two primary metrics: Quantum Cost (QC), determined by the number of non-linear gates, and Logical Depth, which defines the execution speed. Existing literature identifies the HNG gate as the standard for Input-Preserving Reversible Full Adders. HNG gate typically requires a QC of 12 and a logical depth of 5, in the area of classical reversible circuits. This paper proposes the PPKN Gate, a novel design that achieves the same inputpreserving functionality using only one Toffoli gate and five CNOT gates. With a Quantum Cost of 10 and a reduced logical depth of 4, the PPKN gate outperforms the standard HNG gate in both complexity and speed. Furthermore, we present a modular architecture for constructing an n-bit Ripple Carry Adder by cascading PPKN modules.
In the context of modern Very Large-Scale Integration (VLSI) technology, information loss has been a major concern. Logic gates (LG) such as AND, OR, and NOT have been found to result in information loss during their operations. To address this issue, reversible LGs have been created. The development and implementation of a high-speed, efficient full adder circuit employing reversible LGs like Feynman, Toffoli, and Peres gates. The design aims to improve computational and thermal efficiencies. The circuit refarding quantum costs (QC), garbage outputs, and ancillary inputs. The implemented the suggested design in Verilog and verified the entire adder's functionality and efficiency through simulations using the Xilinx Vivado and Xilinx ISE tools. The circuit has a quantum cost of 10 with two outputs of useless and one auxiliary input, according to the researchers, highlighting its opportunities for usage in quantum computing applications andlow-power (dec 84%), high-performance computing systems.