This paper presents the design and implementation of a reversible 4×4 enhanced multiplier using quantum logic principles. The proposed architecture employs Toffoli and Peres gates to realize reversible AND gates and full adders, respectively, ensuring minimal energy dissipation in accordance with Landauer's principle. A layered structure is introduced to improve computation speed and modular scalability while maintaining reversibility. The design effectively reduces garbage outputs and constant inputs, which are critical performance parameters in reversible computing. Simulation results verify the functional correctness of the multiplier and demonstrate its potential for application in quantum computing, low-power VLSI design, and nanotechnology-based systems. The modular nature of the architecture also supports scalability for higher-order multipliers with minimal design overhead.
This paper presents the design and implementation of a reversible 4×4 enhanced multiplier using quantum logic principles. The proposed architecture employs Toffoli and Peres gates to realize reversible AND gates and full adders, respectively, ensuring minimal energy dissipation in accordance with Landauer's principle. A layered structure is introduced to improve computation speed and modular scalability while maintaining reversibility. The design effectively reduces garbage outputs and constant inputs, which are critical performance parameters in reversible computing. Simulation results verify the functional correctness of the multiplier and demonstrate its potential for application in quantum computing, low-power VLSI design, and nanotechnology-based systems. The modular nature of the architecture also supports scalability for higher-order multipliers with minimal design overhead.
Reversible logic plays a crucial role in advancing future VLSI and quantum computing, where the optimization of design parameters like quantum cost, garbage outputs, and circuit complexity is essential. This paper introduces the design and implementation of an efficient 4×4 reversible multiplier on FPGA using Peres and TSG gates. The proposed architecture results in a 31.7 % reduction in quantum cost and enhances TRLIC by up to 30.6% compared to previous designs, while also decreasing garbage outputs and constant inputs. The design has been modeled, simulated, and validated on FPGA to verify its practical viability. Findings indicate that the proposed multiplier strikes a good balance among important parameters, surpassing traditional reversible multipliers in terms of efficiency and scalability. This positions it as a promising option for incorporation into low-power VLSI circuits and quantum arithmetic systems.
In modern Very-Large-Scale Integration (VLSI) technology, managing information loss is a critical challenge. Conventional logic gates, such as AND, OR, and NOT, are prone to data loss during operations, reducing their efficiency for sophisticated applications. Reversible logic gates, which have an equal number of inputs and outputs, offer a solution by preserving data integrity. This paper presents the design and FPGA implementation of an efficient and high-speed full adder circuit utilizing reversible logic gates, namely Feynman, Toffoli, and Peres gates. The design focuses on improving computational efficiency and thermal performance. An analysis of the circuit's quantum cost, garbage outputs, and ancillary inputs reveals its advantages over traditional designs. Proposed design has been realized using Verilog and Synthesize and simulations performed using Xilinx Vivado and Xilinx ISE tools, confirms the functionality and efficiency of the proposed full adder. FPGA implementation of the design has been done using NEXYS A7 (Artix 7 series). The results show that the circuit has a quantum cost of 10, with two garbage outputs and one ancillary input, underscoring its potential for use in low-power, high-performance computing systems and quantum computing applications.
A reconfigurable 16-bit adder utilizing reversible logic is introduced to enhance both energy efficiency and computational performance. The design integrates Toffoli, Peres, and Haghparast–Navi Gate (HNG) to construct optimized full adder units with lower quantum cost, reduced garbage outputs, and minimal constant inputs. A reversible multiplexer is employed to enable seamless switching between Ripple Carry Adder (RCA) and Carry Lookahead Adder (CLA) configurations. While RCA mode supports power-efficient operation, CLA mode enables faster computation, allowing the circuit to adapt to different processing requirements. Performance evaluation is carried out considering propagation delay, power consumption and hardware utilization. The analysis indicates enhanced efficiency over existing reversible adder designs. Due to its adaptable structure and scalable nature, the architecture is appropriate for reversible computing, quantum systems, and low-power VLSI applications.
In the context of modern Very Large-Scale Integration (VLSI) technology, information loss has been a major concern. Logic gates (LG) such as AND, OR, and NOT have been found to result in information loss during their operations. To address this issue, reversible LGs have been created. The development and implementation of a high-speed, efficient full adder circuit employing reversible LGs like Feynman, Toffoli, and Peres gates. The design aims to improve computational and thermal efficiencies. The circuit refarding quantum costs (QC), garbage outputs, and ancillary inputs. The implemented the suggested design in Verilog and verified the entire adder's functionality and efficiency through simulations using the Xilinx Vivado and Xilinx ISE tools. The circuit has a quantum cost of 10 with two outputs of useless and one auxiliary input, according to the researchers, highlighting its opportunities for usage in quantum computing applications andlow-power (dec 84%), high-performance computing systems.
Abstract Reversible gates have been one of the emerging research areas in these days. The reversible gates have several applications in the fields of low power CMOS, DNA computing, optical, nanotechnology etc. Quantum computing is one of the fastest and upcoming nanotechnologies that can implement the digital logical circuits using reversible logic gates. In this paper, CNOT, TOFFOLI, FREDKIN and PERES reversible logic gates have been implemented on IBM quantum computer. An efficient one-bit full adder is going to be proposed using the reversible gates like CNOT and TOFFOLI. Later, a 4x4 multiplier will be developed using the proposed one-bit full adder. The proposed multiplier is proved to perform faster calculations compared to the earlier multipliers. The simulation of the presented modules will be done on IBM Quantum computer and the respective probabilities can be observed for different inputs.
Reversible logic, by enabling computations without loss of information, offers a promising approach to significantly reducing energy dissipation, making it a key technology for low-power and quantum computing systems. Parity-preserving reversible circuits further enhance reliability, enabling fault detection in nanoscale systems. Multiplication, a fundamental operation in computing and signal processing, benefits significantly from efficient reversible designs. However, existing reversible Vedic multipliers often suffer from excessive Quantum Cost (QC), Garbage Outputs (GO), and Constant Inputs (CI). This paper proposes two new 2-bit parity-preserving reversible quantum Vedic multipliers, serving as the foundational block for scalable n-bit multipliers, that are enhanced to reduce quantum metrics without compromising performance. The proposed circuits are simulated using the Quirk tool to test their correct functionality. Comparative analysis shows that the best proposed design outperforms existing architectures on average by 34%, 53%, and 9% in constant inputs, garbage outputs, and quantum cost, respectively, providing a fault-tolerant, cost-efficient, and scalable solution for next-generation quantum computing systems.