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arXiv:2408.06561

A Feasible Design of Elementary Quantum Arithmetic Logic Units for Near-Term Quantum Computers

Junxu Li

Published Aug 13, 2024• 0 citations
arXivHTMLPDF

Abstract

Quantum arithmetic logic units (QALUs) constitute a fundamental component of quantum computing. However, the implementation of QALUs on near-term quantum computers remains a substantial challenge, largely due to the limited connectivity of qubits. In this paper, we propose feasible QALUs, including quantum binary adders, subtractors, multipliers, and dividers, which are designed for near-term quantum computers with qubits arranged in two-dimensional arrays. Additionally, we introduce a feasible quantum arithmetic operation to compute the two's complement representation of signed integers. The proposed QALUs utilize only Pauli-X gates, CNOT gates, and $C\sqrt{X}$ (CSX) gates, and all two-qubit gates are operated between nearest neighbor qubits. Our work demonstrates a viable implementation of QALUs on near-term quantum computers, advancing towards scalable and resource-efficient quantum arithmetic operations.

DOI
10.48550/arxiv.2408.06561

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Quantum arithmetic logic units (QALUs) constitute a fundamental component of quantum computing. However, the implementation of QALUs on near-term quantum computers remains a substantial challenge, largely due to the limited connectivity of qubits. In this paper, we propose feasible QALUs, including quantum binary adders, subtractors, multipliers, and dividers, which are designed for near-term quantum computers with qubits arranged in two-dimensional arrays. Additionally, we introduce a feasible quantum arithmetic operation to compute the two's complement representation of signed integers. The proposed QALUs utilize only Pauli-X gates, CNOT gates, and CXC\sqrt{X}CX​ (CSX) gates, and all two-qubit gates are operated between nearest neighbor qubits. Our work demonstrates a viable implementation of QALUs on near-term quantum computers, advancing towards scalable and resource-efficient quantum arithmetic operations.
Abstract Quantum arithmetic logic units (QALUs) are essential building blocks for quantum computation, yet their realization on near-term hardware is hindered by restricted qubit connectivity. Here we present hardware-efficient quantum arithmetic logic units (QALUs), including quantum adders, subtractors, multipliers, and dividers, for quantum computers with square lattice architectures. Our constructions rely solely on Pauli-X, CNOT, and controlled- X (CSX) gates, with all two-qubit operations confined to nearest-neitablghbor qubits. In addition, we introduce the quantum algorithm to obtain the two’s-complement representation of signed integers. These results demonstrate a scalable and hardware-efficient implementation of QALUs on square-grid quantum hardware, paving the way for more complex quantum algorithms on realistic devices.
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Abstract This study proposes and construct a primitive quantum arithmetic logic unit (qALU) based on the quantum Fourier transform (QFT). The qALU is capable of performing arithmetic ADD (addition) and logic NAND gate operations. It designs a scalable quantum circuit and presents the circuits for driving ADD and NAND operations on two‐input and four‐input quantum channels, respectively. By comparing the required number of quantum gates for serial and parallel architectures in executing arithmetic addition, it evaluates the performance. It also execute the proposed quantum Fourier transform‐based qALU design on real quantum processor hardware provided by IBM. The results demonstrate that the proposed circuit can perform arithmetic and logic operations with a high success rate. Furthermore, it discusses in detail the potential implementations of the qALU circuit in the field of computer science, highlighting the possibility of constructing a soft‐core processor on a quantum processing unit.