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International Conference on Data Science and Network Security (ICDSNS)

Quantum-Dot Cellular Automata for Arithmetic Circuits: A Novel Approach to Adders, Subtractors and Comparators

B. L. Lavanya, Durga Prasad

Published Jul 25, 2025• 1 citation

Abstract

The design of arithmetic and logical unit is a crucial block schematic of quantum computing, which has gained popularity in recent years. While division is a successive subtraction, a logical multiplier employs the technique of successive addition, which are the essential blocks of the quantum computing. The key components including comparator design, adders, and subtractors are considered with the help of Quantum-Dot Cellular Automata (QCA) in this work. Such essential blocks of the Arithmetic Logic Unit (ALU) are designed, implemented, and tested in the simulation using QCADesigner version 2.0.3. The results are found to be appealing with the standard truth tables of the above logical circuits. Hence, the designs could be utilized in the practical applications of Internet of Things, Block chains and Cryptographic solutions catering to the challenges of industry, healthcare and finance sectors. Addressing challenges such as a reduced number of qubits and complexity reduction could make way for more robust and practical ALU designs in QCA-based quantum systems. In the proposed novel work, the number of qubits required has been reduced to 24, offering a notable reduction compared to several recent approaches. Hence, the novelty of the work lies in the architectural-level reorganization and logic-level minimization strategy, which collectively enable a significant reduction in design complexity (up to 93%) without introducing additional fabrication or simulation overhead, optimizing clock zone assignments to enhance timing efficiency.

DOI: 10.1109/icdsns65743.2025.11168645

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The effects of quantum mechanics dominate nanoscale devices, where Moore’s law no longer holds true. Additionally, with the recent rapid development of quantum computers, the development of reversible gates to overcome the problems of energy and information loss and the nano-level quantum-dot cellular automata (QCA) technology to efficiently implement them are in the spotlight. In this study, a full adder-subtractor, a core operation of the arithmetic and logic unit (ALU), the most important hardware device in computer operations, is implemented as a circuit capable of reversible operation using QCA-based reversible gates. The proposed circuit consists of one reversible QCA gate and two Feynman gates and is designed as a multi-layer structure for efficient use of area and minimization of delay. The proposed circuit is tested on QCADesigner 2.0.3 and QCADesigner-E 2.2 and shows the best performance and lowest energy dissipation. In particular, it shows tremendous improvement rates of 180% and 562% in two representative standard design cost indicators compared to the best existing studies, and also shows the highest circuit average output polarization.

Quantum Computing is an emerging technology that offers significant advantages over classical computation with regard to speed, circuit density and heat dissipation. These future computers employs the reversibility property to make the computations faster. In contrast to conventional computers, quantum computers can restore the input bits uniquely after the logic block is evaluated, as input and output bits exhibits one-to-one correlation. To make the best use of this technology with existing limitations ,this paper focuses on building quantum adder circuits with less gate-count using IBM Qiskit. The Qiskit output should be analogous to the conventional output. Also to analyze the working of quantum circuits in layout structure, "Quantum Dot Cellular Automata(QCA)" technology is employed. In this approach, the reversible adder design is executed using the QCA designer tool with efficient formulation and novel arrangement of QCA cells. The proposed design has better complexity than other previous works with a declined number of gate-count, cell-count, delay and area.

Reversible logic is becoming increasingly important with the rise of technologies like quantum computing, as it retains information during computation and maintains a direct match between each input and its corresponding output. Quantum circuits are inherently reversible and the best computational model in quantum computing systems. Quantum computers require quantum processors. A critical component of any computer's processor is the arithmetic component, that handles binary operations like addition, subtraction, multiplication, and division. Notably, multiplication can be accomplished by repeatedly adding, while division can be carried out by repeatedly subtracting. This paper proposes a new design of quantum-controlled adder/subtractor (QCAS) with efficient quantum criteria like delay, quantum cost, number of ancilla and of garbage outputs. We propose a quantum reversible controlled full adder/subtractor block which is applied to construct an n-bit quantum adder/subtractor circuit. The proposed circuit is simulated using the Quirk online tool and the result confirms the accuracy of the design. This design achieves 28.5% and 61.3% improvement in delay and garbage outputs, and 14% and 41.2% increase in quantum cost and constant input, compared to its counterpart, respectively.

Abstract Quantum arithmetic logic units (QALUs) are essential building blocks for quantum computation, yet their realization on near-term hardware is hindered by restricted qubit connectivity. Here we present hardware-efficient quantum arithmetic logic units (QALUs), including quantum adders, subtractors, multipliers, and dividers, for quantum computers with square lattice architectures. Our constructions rely solely on Pauli-X, CNOT, and controlled- X (CSX) gates, with all two-qubit operations confined to nearest-neitablghbor qubits. In addition, we introduce the quantum algorithm to obtain the two’s-complement representation of signed integers. These results demonstrate a scalable and hardware-efficient implementation of QALUs on square-grid quantum hardware, paving the way for more complex quantum algorithms on realistic devices.

In this paper, an n-bit Quantum Binary Adder-Subtractor (QBAS) is designed using quantum logic gates using IBM Qiskit. A comprehensive understanding of the principles of quantum computing and quantum logic gates is also provided. As the fundamental module of a binary adder-subtractor circuit is a full adder, various designs of quantum full adders (QFAs) from the literature are investigated on various aspects to deliberately choose the best quantum full adder suitable for QBAS application. A QBAS circuit is thus designed using the selected QFA, analyzed and tested for its ability to replicate the output of its classical counterpart. The results obtained here will aid researchers in the design of Quantum Arithmetic Logic Units (QALUs), Quantum multipliers, dividers, and other scalable adder circuits. The proposed circuits and its results shown here expected to pave the way for design of compact and state of the art quantum adders with reduced number of qubits, quantum cost.

Quantum arithmetic logic units (QALUs) constitute a fundamental component of quantum computing. However, the implementation of QALUs on near-term quantum computers remains a substantial challenge, largely due to the limited connectivity of qubits. In this paper, we propose feasible QALUs, including quantum binary adders, subtractors, multipliers, and dividers, which are designed for near-term quantum computers with qubits arranged in two-dimensional arrays. Additionally, we introduce a feasible quantum arithmetic operation to compute the two's complement representation of signed integers. The proposed QALUs utilize only Pauli-X gates, CNOT gates, and

C\sqrt{X}

(CSX) gates, and all two-qubit gates are operated between nearest neighbor qubits. Our work demonstrates a viable implementation of QALUs on near-term quantum computers, advancing towards scalable and resource-efficient quantum arithmetic operations.