Multi-Layer QCA Reversible Full Adder-Subtractor Using Reversible Gates for Reliable Information Transfer and Minimal Power Dissipation on Universal Quantum Computer
The effects of quantum mechanics dominate nanoscale devices, where Moore’s law no longer holds true. Additionally, with the recent rapid development of quantum computers, the development of reversible gates to overcome the problems of energy and information loss and the nano-level quantum-dot cellular automata (QCA) technology to efficiently implement them are in the spotlight. In this study, a full adder-subtractor, a core operation of the arithmetic and logic unit (ALU), the most important hardware device in computer operations, is implemented as a circuit capable of reversible operation using QCA-based reversible gates. The proposed circuit consists of one reversible QCA gate and two Feynman gates and is designed as a multi-layer structure for efficient use of area and minimization of delay. The proposed circuit is tested on QCADesigner 2.0.3 and QCADesigner-E 2.2 and shows the best performance and lowest energy dissipation. In particular, it shows tremendous improvement rates of 180% and 562% in two representative standard design cost indicators compared to the best existing studies, and also shows the highest circuit average output polarization.
The effects of quantum mechanics dominate nanoscale devices, where Moore’s law no longer holds true. Additionally, with the recent rapid development of quantum computers, the development of reversible gates to overcome the problems of energy and information loss and the nano-level quantum-dot cellular automata (QCA) technology to efficiently implement them are in the spotlight. In this study, a full adder-subtractor, a core operation of the arithmetic and logic unit (ALU), the most important hardware device in computer operations, is implemented as a circuit capable of reversible operation using QCA-based reversible gates. The proposed circuit consists of one reversible QCA gate and two Feynman gates and is designed as a multi-layer structure for efficient use of area and minimization of delay. The proposed circuit is tested on QCADesigner 2.0.3 and QCADesigner-E 2.2 and shows the best performance and lowest energy dissipation. In particular, it shows tremendous improvement rates of 180% and 562% in two representative standard design cost indicators compared to the best existing studies, and also shows the highest circuit average output polarization.
The design of arithmetic and logical unit is a crucial block schematic of quantum computing, which has gained popularity in recent years. While division is a successive subtraction, a logical multiplier employs the technique of successive addition, which are the essential blocks of the quantum computing. The key components including comparator design, adders, and subtractors are considered with the help of Quantum-Dot Cellular Automata (QCA) in this work. Such essential blocks of the Arithmetic Logic Unit (ALU) are designed, implemented, and tested in the simulation using QCADesigner version 2.0.3. The results are found to be appealing with the standard truth tables of the above logical circuits. Hence, the designs could be utilized in the practical applications of Internet of Things, Block chains and Cryptographic solutions catering to the challenges of industry, healthcare and finance sectors. Addressing challenges such as a reduced number of qubits and complexity reduction could make way for more robust and practical ALU designs in QCA-based quantum systems. In the proposed novel work, the number of qubits required has been reduced to 24, offering a notable reduction compared to several recent approaches. Hence, the novelty of the work lies in the architectural-level reorganization and logic-level minimization strategy, which collectively enable a significant reduction in design complexity (up to 93%) without introducing additional fabrication or simulation overhead, optimizing clock zone assignments to enhance timing efficiency.
Quantum Computing is an emerging technology that offers significant advantages over classical computation with regard to speed, circuit density and heat dissipation. These future computers employs the reversibility property to make the computations faster. In contrast to conventional computers, quantum computers can restore the input bits uniquely after the logic block is evaluated, as input and output bits exhibits one-to-one correlation. To make the best use of this technology with existing limitations ,this paper focuses on building quantum adder circuits with less gate-count using IBM Qiskit. The Qiskit output should be analogous to the conventional output. Also to analyze the working of quantum circuits in layout structure, "Quantum Dot Cellular Automata(QCA)" technology is employed. In this approach, the reversible adder design is executed using the QCA designer tool with efficient formulation and novel arrangement of QCA cells. The proposed design has better complexity than other previous works with a declined number of gate-count, cell-count, delay and area.
Quantum processors are a central element of a quantum computer. Processors are responsible for performing the fundamental operations like addition, subtraction, etc. of any computer. This also involves the arithmetic unit and has a different configuration for the quantum computer than for a classical computer. Multiplication is essentially repeated addition and division is repeated subtraction. But for quantum computer other methodologies have to be used for arithmetic. In this paper a Quantum Full Adder/Subtractor Circuit, using the reversible Peres Gate, R3Gate and a NOT Gate, is proposed. So, the proposed design can be used for both modes, adder and subtractor on quantum operation. The authors have also compared proposed design with other designs reported, in terms of Gate count, Garbage bits, Quantum cost and Delay. The authors have achieved a 62.5% increment in delay and a low power computing reversible logic in which the computation is faster and energy efficient. Using IBM Qiskit, the authors have created and tested the circuit.
In the current scenario, power consumption, speed, size and heat dissipation are the huge challenge in the semiconductor industries. When the size of the single computing element is reduced then the speed can be improved and also if the power dissipation is reduced then the heat dissipation will be less. The possible solution for these two problems is the Reversible Logic and Quantum Cellular Automata (QCA). The Reversible Logic is considered to be the promising technology to the future Quantum computer technologies. The Reversible Logic gates prune the power dissipation to a larger extent. In this paper Novel Reversible Gates are proposed with Reversibility and Universality. The Arithmetic and Logic Unit (ALU) is designed with the proposed Reversible Gates in Reversible Logic. The designed Arithmetic and Logic unit is evaluated in QCA with the required specifications. The Arithmetic and Logic Unit is designed by setting the control inputs for each unit. The parameters taken into account are Quantum Cost (QC), Garbage Outputs (GO), Constant Inputs (CI), Area, Number of Cells and Simulation Time. The proposed ALU adopting Novel gates finds utilization in low power applications. Also it can be used as the module in the Quantum computers due to its reduced Quantum Cost and Garbage outputs. The Proposed design extends its applications over Quantum Computing, Optical Computing, Nanotechnology and DNA mapping.
Reversible arithmetic and logic unit (ALU) is a necessary part of quantum computing. In this work, we present improved designs of reversible half and full addition and subtraction circuits. The proposed designs are based on a universal one type gate (G gate library). The G gate library can generate all possible permutations of the symmetric group. The presented designs are multi-function circuits that are capable of performing additional logical operations. We achieve a reduction in the quantum cost, gate count, number of constant inputs, and delay with zero garbage, compared to relevant results obtained by others. The experimental results using IBM Quantum Experience (IBM Q) illustrate the success probability of the proposed designs.
Reversible logic is becoming increasingly important with the rise of technologies like quantum computing, as it retains information during computation and maintains a direct match between each input and its corresponding output. Quantum circuits are inherently reversible and the best computational model in quantum computing systems. Quantum computers require quantum processors. A critical component of any computer's processor is the arithmetic component, that handles binary operations like addition, subtraction, multiplication, and division. Notably, multiplication can be accomplished by repeatedly adding, while division can be carried out by repeatedly subtracting. This paper proposes a new design of quantum-controlled adder/subtractor (QCAS) with efficient quantum criteria like delay, quantum cost, number of ancilla and of garbage outputs. We propose a quantum reversible controlled full adder/subtractor block which is applied to construct an n-bit quantum adder/subtractor circuit. The proposed circuit is simulated using the Quirk online tool and the result confirms the accuracy of the design. This design achieves 28.5% and 61.3% improvement in delay and garbage outputs, and 14% and 41.2% increase in quantum cost and constant input, compared to its counterpart, respectively.