Reversible arithmetic and logic unit (ALU) is a necessary part of quantum computing. In this work, we present improved designs of reversible half and full addition and subtraction circuits. The proposed designs are based on a universal one type gate (G gate library). The G gate library can generate all possible permutations of the symmetric group. The presented designs are multi-function circuits that are capable of performing additional logical operations. We achieve a reduction in the quantum cost, gate count, number of constant inputs, and delay with zero garbage, compared to relevant results obtained by others. The experimental results using IBM Quantum Experience (IBM Q) illustrate the success probability of the proposed designs.
Reversible arithmetic and logic unit (ALU) is a necessary part of quantum computing. In this work, we present improved designs of reversible half and full addition and subtraction circuits. The proposed designs are based on a universal one type gate (G gate library). The G gate library can generate all possible permutations of the symmetric group. The presented designs are multi-function circuits that are capable of performing additional logical operations. We achieve a reduction in the quantum cost, gate count, number of constant inputs, and delay with zero garbage, compared to relevant results obtained by others. The experimental results using IBM Quantum Experience (IBM Q) illustrate the success probability of the proposed designs.
Quantum processors are a central element of a quantum computer. Processors are responsible for performing the fundamental operations like addition, subtraction, etc. of any computer. This also involves the arithmetic unit and has a different configuration for the quantum computer than for a classical computer. Multiplication is essentially repeated addition and division is repeated subtraction. But for quantum computer other methodologies have to be used for arithmetic. In this paper a Quantum Full Adder/Subtractor Circuit, using the reversible Peres Gate, R3Gate and a NOT Gate, is proposed. So, the proposed design can be used for both modes, adder and subtractor on quantum operation. The authors have also compared proposed design with other designs reported, in terms of Gate count, Garbage bits, Quantum cost and Delay. The authors have achieved a 62.5% increment in delay and a low power computing reversible logic in which the computation is faster and energy efficient. Using IBM Qiskit, the authors have created and tested the circuit.
The power consumption in classical computers has grown to be a critical issue. Thus, quantum computers have become a promising alternative to classical computers for more processing power and lower energy consumption. Reversible gates are important for building the quantum computers. Reversible circuits have various applications, such as digital signal processing, optical computing, quantum computing, etc. The design and synthesis of reversible gates and circuits have grown in popularity and attracted the attention of many researchers. The adder and subtractor are important computation blocks for the structure of the Arithmetic Logic Unit (ALU). In this paper, a design of reversible binary half and full adders and subtractors using reversible logic gates is proposed. The TR (Thapliyal Ranganathan) and Peres gates are used to construct the reversible half adder and subtractor circuit. Meanwhile, the Double Peres Gate (DPG), Fredkin, and NOT gates are used to build the reversible 1-bit full adder and subtractor circuit. The designs are optimized in terms of number of gates, constant inputs, garbage outputs, and quantum cost. The truth table representation and the Binary Decision Diagram (BDD) synthesis method are used to represent and synthesize the circuits, respectively. The circuits are synthesized and simulated using the Verilog Hardware Description Language code and Xilinx ISE 14.7. The results show that the proposed designs achieve the lowest quantum cost in both half adder/subtractor and full adder/subtractor. As the half adder/subtractor has six quantum cost and the full adder/subtractor has nine quantum cost.
This paper proposed the design and development of reversible cost-efficient innovative quantum dual-full adder and subtractor or QD-FAS circuit using quantum gate. The proposed circuit can be used as full adder and full subtractor simultaneously, which is designed using double Peres gate or DPG and Feynman gate or FG. The quantum cost, garbage output and constant input of the QD-FAS is 8, 1 and 1. Which is better w.r.t previously reported work. The QD-FAS circuit, as proposed, includes shared sum and difference terminals, as well as a carry-out and a borrow output terminal. Notably, this innovation showcases a remarkable 27.27% reduction in quantum cost. The improvement in garbage output is even more striking, showing a 50% enhancement. When assessing the overall advancement in quantum cost, it falls within the range of 27.27% to 66.66%. To confirm the viability of this design, extensive testing is carried out using the IBM Qiskit simulator. This design holds significant importance in a variety of applications, including quantum computing, cryptography, and the realm of reversible Arithmetic Logic Units (ALU).
The effects of quantum mechanics dominate nanoscale devices, where Moore’s law no longer holds true. Additionally, with the recent rapid development of quantum computers, the development of reversible gates to overcome the problems of energy and information loss and the nano-level quantum-dot cellular automata (QCA) technology to efficiently implement them are in the spotlight. In this study, a full adder-subtractor, a core operation of the arithmetic and logic unit (ALU), the most important hardware device in computer operations, is implemented as a circuit capable of reversible operation using QCA-based reversible gates. The proposed circuit consists of one reversible QCA gate and two Feynman gates and is designed as a multi-layer structure for efficient use of area and minimization of delay. The proposed circuit is tested on QCADesigner 2.0.3 and QCADesigner-E 2.2 and shows the best performance and lowest energy dissipation. In particular, it shows tremendous improvement rates of 180% and 562% in two representative standard design cost indicators compared to the best existing studies, and also shows the highest circuit average output polarization.
Reversible logic is becoming increasingly important with the rise of technologies like quantum computing, as it retains information during computation and maintains a direct match between each input and its corresponding output. Quantum circuits are inherently reversible and the best computational model in quantum computing systems. Quantum computers require quantum processors. A critical component of any computer's processor is the arithmetic component, that handles binary operations like addition, subtraction, multiplication, and division. Notably, multiplication can be accomplished by repeatedly adding, while division can be carried out by repeatedly subtracting. This paper proposes a new design of quantum-controlled adder/subtractor (QCAS) with efficient quantum criteria like delay, quantum cost, number of ancilla and of garbage outputs. We propose a quantum reversible controlled full adder/subtractor block which is applied to construct an n-bit quantum adder/subtractor circuit. The proposed circuit is simulated using the Quirk online tool and the result confirms the accuracy of the design. This design achieves 28.5% and 61.3% improvement in delay and garbage outputs, and 14% and 41.2% increase in quantum cost and constant input, compared to its counterpart, respectively.
The ternary quantum circuit is very useful in arithmetic and logic operations. This circuit has several advantages as it reduces power dissipation, step time, etc. Adder circuit is the main block of various computing units and for several other complex computer designs. In this current paper, we have used generalized ternary gate (GTG) and reversible gates for the synthesis of reversible half adder and a full adder circuits. The presented designs offer reduced constant inputs and less quantum cost, compared to existing designs. Our proposed design allows a reduction of 40% of the cost and 25% of the number of gates used.