In this paper, an n-bit Quantum Binary Adder-Subtractor (QBAS) is designed using quantum logic gates using IBM Qiskit. A comprehensive understanding of the principles of quantum computing and quantum logic gates is also provided. As the fundamental module of a binary adder-subtractor circuit is a full adder, various designs of quantum full adders (QFAs) from the literature are investigated on various aspects to deliberately choose the best quantum full adder suitable for QBAS application. A QBAS circuit is thus designed using the selected QFA, analyzed and tested for its ability to replicate the output of its classical counterpart. The results obtained here will aid researchers in the design of Quantum Arithmetic Logic Units (QALUs), Quantum multipliers, dividers, and other scalable adder circuits. The proposed circuits and its results shown here expected to pave the way for design of compact and state of the art quantum adders with reduced number of qubits, quantum cost.
In this paper, an n-bit Quantum Binary Adder-Subtractor (QBAS) is designed using quantum logic gates using IBM Qiskit. A comprehensive understanding of the principles of quantum computing and quantum logic gates is also provided. As the fundamental module of a binary adder-subtractor circuit is a full adder, various designs of quantum full adders (QFAs) from the literature are investigated on various aspects to deliberately choose the best quantum full adder suitable for QBAS application. A QBAS circuit is thus designed using the selected QFA, analyzed and tested for its ability to replicate the output of its classical counterpart. The results obtained here will aid researchers in the design of Quantum Arithmetic Logic Units (QALUs), Quantum multipliers, dividers, and other scalable adder circuits. The proposed circuits and its results shown here expected to pave the way for design of compact and state of the art quantum adders with reduced number of qubits, quantum cost.
Quantum processors are a central element of a quantum computer. Processors are responsible for performing the fundamental operations like addition, subtraction, etc. of any computer. This also involves the arithmetic unit and has a different configuration for the quantum computer than for a classical computer. Multiplication is essentially repeated addition and division is repeated subtraction. But for quantum computer other methodologies have to be used for arithmetic. In this paper a Quantum Full Adder/Subtractor Circuit, using the reversible Peres Gate, R3Gate and a NOT Gate, is proposed. So, the proposed design can be used for both modes, adder and subtractor on quantum operation. The authors have also compared proposed design with other designs reported, in terms of Gate count, Garbage bits, Quantum cost and Delay. The authors have achieved a 62.5% increment in delay and a low power computing reversible logic in which the computation is faster and energy efficient. Using IBM Qiskit, the authors have created and tested the circuit.
The power consumption in classical computers has grown to be a critical issue. Thus, quantum computers have become a promising alternative to classical computers for more processing power and lower energy consumption. Reversible gates are important for building the quantum computers. Reversible circuits have various applications, such as digital signal processing, optical computing, quantum computing, etc. The design and synthesis of reversible gates and circuits have grown in popularity and attracted the attention of many researchers. The adder and subtractor are important computation blocks for the structure of the Arithmetic Logic Unit (ALU). In this paper, a design of reversible binary half and full adders and subtractors using reversible logic gates is proposed. The TR (Thapliyal Ranganathan) and Peres gates are used to construct the reversible half adder and subtractor circuit. Meanwhile, the Double Peres Gate (DPG), Fredkin, and NOT gates are used to build the reversible 1-bit full adder and subtractor circuit. The designs are optimized in terms of number of gates, constant inputs, garbage outputs, and quantum cost. The truth table representation and the Binary Decision Diagram (BDD) synthesis method are used to represent and synthesize the circuits, respectively. The circuits are synthesized and simulated using the Verilog Hardware Description Language code and Xilinx ISE 14.7. The results show that the proposed designs achieve the lowest quantum cost in both half adder/subtractor and full adder/subtractor. As the half adder/subtractor has six quantum cost and the full adder/subtractor has nine quantum cost.
Reversible logic is becoming increasingly important with the rise of technologies like quantum computing, as it retains information during computation and maintains a direct match between each input and its corresponding output. Quantum circuits are inherently reversible and the best computational model in quantum computing systems. Quantum computers require quantum processors. A critical component of any computer's processor is the arithmetic component, that handles binary operations like addition, subtraction, multiplication, and division. Notably, multiplication can be accomplished by repeatedly adding, while division can be carried out by repeatedly subtracting. This paper proposes a new design of quantum-controlled adder/subtractor (QCAS) with efficient quantum criteria like delay, quantum cost, number of ancilla and of garbage outputs. We propose a quantum reversible controlled full adder/subtractor block which is applied to construct an n-bit quantum adder/subtractor circuit. The proposed circuit is simulated using the Quirk online tool and the result confirms the accuracy of the design. This design achieves 28.5% and 61.3% improvement in delay and garbage outputs, and 14% and 41.2% increase in quantum cost and constant input, compared to its counterpart, respectively.
Quantum arithmetic logic units (QALUs) constitute a fundamental component of quantum computing. However, the implementation of QALUs on near-term quantum computers remains a substantial challenge, largely due to the limited connectivity of qubits. In this paper, we propose feasible QALUs, including quantum binary adders, subtractors, multipliers, and dividers, which are designed for near-term quantum computers with qubits arranged in two-dimensional arrays. Additionally, we introduce a feasible quantum arithmetic operation to compute the two's complement representation of signed integers. The proposed QALUs utilize only Pauli-X gates, CNOT gates, and CX (CSX) gates, and all two-qubit gates are operated between nearest neighbor qubits. Our work demonstrates a viable implementation of QALUs on near-term quantum computers, advancing towards scalable and resource-efficient quantum arithmetic operations.
This paper proposed the design and development of reversible cost-efficient innovative quantum dual-full adder and subtractor or QD-FAS circuit using quantum gate. The proposed circuit can be used as full adder and full subtractor simultaneously, which is designed using double Peres gate or DPG and Feynman gate or FG. The quantum cost, garbage output and constant input of the QD-FAS is 8, 1 and 1. Which is better w.r.t previously reported work. The QD-FAS circuit, as proposed, includes shared sum and difference terminals, as well as a carry-out and a borrow output terminal. Notably, this innovation showcases a remarkable 27.27% reduction in quantum cost. The improvement in garbage output is even more striking, showing a 50% enhancement. When assessing the overall advancement in quantum cost, it falls within the range of 27.27% to 66.66%. To confirm the viability of this design, extensive testing is carried out using the IBM Qiskit simulator. This design holds significant importance in a variety of applications, including quantum computing, cryptography, and the realm of reversible Arithmetic Logic Units (ALU).
Quantum computing is an emerging computational paradigm that represents and processes information using quantum states. This paper presents the implementation and simulation of a Quantum Half Adder using the IBM Qiskit framework. The proposed circuit performs one-bit binary addition and produces two outputs, SUM and CARRY, through reversible quantum operations. Classical input values are encoded into quantum states using Pauli-X gates. Controlled-NOT (CNOT) gates are used to realize the XOR relationship required for SUM generation, while a Toffoli (CCNOT) gate realizes the AND relationship required for CARRY generation. The complete design is implemented in Python and executed using the Qiskit Aer Simulator. Four possible input combinations are evaluated and the measured outputs are compared with the expected Half Adder truth table. Circuit visualization, terminal output, and measurement histograms are used to verify the operation. The results show that the simulated circuit produces the expected SUM and CARRY values for all input combinations. The work provides a simple practical model for understanding reversible quantum computation, quantum gates, and Qiskit-based quantum circuit simulation.