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Electronics Letters

Quantum full adder and subtractor

Kai-Wen Cheng, Chien‐Cheng Tseng

Published Oct 24, 2002• 48 citations
Publisher

Abstract

The designs of quantum full adder (QFA) and quantum full subtractor (QFS) are investigated. First, the 1-bit QFA and 1-bit QFS are designed according to the classical truth tables. The adder and subtractor for two n-bits numbers are then separately constructed from n 1-bit QFAs and QFSs. The number of elementary quantum gates to accomplish the design of n-bits adder and subtractor are 4n and 8n, respectively.

DOI
10.1049/el:20020949

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•Apr 1, 2016•7 citations
The designs of quantum full adder (QFA) and quantum full subtractor (QFS) are investigated. First, the 1-bit QFA and 1-bit QFS are designed according to the classical truth tables. The adder and subtractor for two n-bits numbers are then separately constructed from n 1-bit QFAs and QFSs. The number of elementary quantum gates to accomplish the design of n-bits adder and subtractor are 4n and 8n, respectively.
In this paper, an n-bit Quantum Binary Adder-Subtractor (QBAS) is designed using quantum logic gates using IBM Qiskit. A comprehensive understanding of the principles of quantum computing and quantum logic gates is also provided. As the fundamental module of a binary adder-subtractor circuit is a full adder, various designs of quantum full adders (QFAs) from the literature are investigated on various aspects to deliberately choose the best quantum full adder suitable for QBAS application. A QBAS circuit is thus designed using the selected QFA, analyzed and tested for its ability to replicate the output of its classical counterpart. The results obtained here will aid researchers in the design of Quantum Arithmetic Logic Units (QALUs), Quantum multipliers, dividers, and other scalable adder circuits. The proposed circuits and its results shown here expected to pave the way for design of compact and state of the art quantum adders with reduced number of qubits, quantum cost.
The power consumption in classical computers has grown to be a critical issue. Thus, quantum computers have become a promising alternative to classical computers for more processing power and lower energy consumption. Reversible gates are important for building the quantum computers. Reversible circuits have various applications, such as digital signal processing, optical computing, quantum computing, etc. The design and synthesis of reversible gates and circuits have grown in popularity and attracted the attention of many researchers. The adder and subtractor are important computation blocks for the structure of the Arithmetic Logic Unit (ALU). In this paper, a design of reversible binary half and full adders and subtractors using reversible logic gates is proposed. The TR (Thapliyal Ranganathan) and Peres gates are used to construct the reversible half adder and subtractor circuit. Meanwhile, the Double Peres Gate (DPG), Fredkin, and NOT gates are used to build the reversible 1-bit full adder and subtractor circuit. The designs are optimized in terms of number of gates, constant inputs, garbage outputs, and quantum cost. The truth table representation and the Binary Decision Diagram (BDD) synthesis method are used to represent and synthesize the circuits, respectively. The circuits are synthesized and simulated using the Verilog Hardware Description Language code and Xilinx ISE 14.7. The results show that the proposed designs achieve the lowest quantum cost in both half adder/subtractor and full adder/subtractor. As the half adder/subtractor has six quantum cost and the full adder/subtractor has nine quantum cost.
Reversible logic is becoming increasingly important with the rise of technologies like quantum computing, as it retains information during computation and maintains a direct match between each input and its corresponding output. Quantum circuits are inherently reversible and the best computational model in quantum computing systems. Quantum computers require quantum processors. A critical component of any computer's processor is the arithmetic component, that handles binary operations like addition, subtraction, multiplication, and division. Notably, multiplication can be accomplished by repeatedly adding, while division can be carried out by repeatedly subtracting. This paper proposes a new design of quantum-controlled adder/subtractor (QCAS) with efficient quantum criteria like delay, quantum cost, number of ancilla and of garbage outputs. We propose a quantum reversible controlled full adder/subtractor block which is applied to construct an n-bit quantum adder/subtractor circuit. The proposed circuit is simulated using the Quirk online tool and the result confirms the accuracy of the design. This design achieves 28.5% and 61.3% improvement in delay and garbage outputs, and 14% and 41.2% increase in quantum cost and constant input, compared to its counterpart, respectively.
In this study, we construct the quantum reversible counterparts of the logical AND, OR, XOR, NOR, and NAND gates. We utilize a quantum Fourier transform (QFT)-based adder circuit that replicates the functionality of a digital half-adder, which computes the sum and carry of two input bits using XOR and AND gates, respectively. To realize different logic gate operations, we apply pre- and post-processing to the QFT-adder using quantum gates, leveraging Boolean algebra properties to enable conversions between various logical functions. Although the number of elementary quantum logic gates increases for a small number of inputs-making the approach appear inefficient at first glance-the overall required qubit count is reduced compared to non-QFT-based designs as the number of inputs increases.
Ternary quantum logic plays a very important role for building high speed and efficient futuristic computers. It has several advantages over classical computing and binary quantum circuits. In this paper, the realization of basic ternary circuits for adder/subtractor, encoder and priority encoder are proposed and designed. These circuits are very essential for the construction of various computational units of quantum computers and other complex computational systems. Design of reversible circuits can be improved by reducing the quantum circuit cost. This paper uses some elementary components and typical ternary gates (generalized ternary gate, M-S gate etc.) to perform arithmetic addition, subtraction and encoding operations. Finally, it evaluates the optimum cost for each circuit.