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IEEE International Symposium on Multiple-Valued Logic (ISMVL)

Design of a Compact Ternary Parallel Adder/Subtractor Circuit in Quantum Computing

Nusrat Jahan Lisa, Hafiz Md. Hasan Babu

Published May 1, 2015• 16 citations
Publisher

Abstract

In this paper, we present an optimized design for the quantum ternary adder/subtract or circuit. We propose the design of quantum Ternary Peres Gate (TPG). The design of our proposed quantum ternary adder/subtract or circuit consists of two parts: a) Firstly, it has the design of a quantum ternary full-adder circuit using the proposed TPG gates, and b) Secondly, it designs the proposed adder/subtract or circuit by using the constructed full-adder in a) and M-S gates. We also propose a heuristic to design a compact ternary adder/subtract or circuit. Our circuits perform much better than the existing ones.

DOI
10.1109/ismvl.2015.23

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In this paper, we present an optimized design for the quantum ternary adder/subtract or circuit. We propose the design of quantum Ternary Peres Gate (TPG). The design of our proposed quantum ternary adder/subtract or circuit consists of two parts: a) Firstly, it has the design of a quantum ternary full-adder circuit using the proposed TPG gates, and b) Secondly, it designs the proposed adder/subtract or circuit by using the constructed full-adder in a) and M-S gates. We also propose a heuristic to design a compact ternary adder/subtract or circuit. Our circuits perform much better than the existing ones.
Ternary quantum logic plays a very important role for building high speed and efficient futuristic computers. It has several advantages over classical computing and binary quantum circuits. In this paper, the realization of basic ternary circuits for adder/subtractor, encoder and priority encoder are proposed and designed. These circuits are very essential for the construction of various computational units of quantum computers and other complex computational systems. Design of reversible circuits can be improved by reducing the quantum circuit cost. This paper uses some elementary components and typical ternary gates (generalized ternary gate, M-S gate etc.) to perform arithmetic addition, subtraction and encoding operations. Finally, it evaluates the optimum cost for each circuit.
In this paper, we propose two new designs for the barrel shifter: i) a quantum ternary unidirectional barrel shifter (Design I) and ii) a quantum ternary bidirectional barrel shifter (Design II). We present the design of Ternary Peres Gate (TPG). The designs of ternary barrel shifters show that circuits are composed of proposed Ternary Peres Gates, Modified Fredkin Gates and Ternary Feynman Gates. A new technique to calculate the ternary quantum gate calculation complexity of ternary circuits has been proposed in the paper. Our circuits perform better than the existing ones in terms of quantum gates, garbage outputs and ternary quantum gate calculation complexity.
The power consumption in classical computers has grown to be a critical issue. Thus, quantum computers have become a promising alternative to classical computers for more processing power and lower energy consumption. Reversible gates are important for building the quantum computers. Reversible circuits have various applications, such as digital signal processing, optical computing, quantum computing, etc. The design and synthesis of reversible gates and circuits have grown in popularity and attracted the attention of many researchers. The adder and subtractor are important computation blocks for the structure of the Arithmetic Logic Unit (ALU). In this paper, a design of reversible binary half and full adders and subtractors using reversible logic gates is proposed. The TR (Thapliyal Ranganathan) and Peres gates are used to construct the reversible half adder and subtractor circuit. Meanwhile, the Double Peres Gate (DPG), Fredkin, and NOT gates are used to build the reversible 1-bit full adder and subtractor circuit. The designs are optimized in terms of number of gates, constant inputs, garbage outputs, and quantum cost. The truth table representation and the Binary Decision Diagram (BDD) synthesis method are used to represent and synthesize the circuits, respectively. The circuits are synthesized and simulated using the Verilog Hardware Description Language code and Xilinx ISE 14.7. The results show that the proposed designs achieve the lowest quantum cost in both half adder/subtractor and full adder/subtractor. As the half adder/subtractor has six quantum cost and the full adder/subtractor has nine quantum cost.
Ternary quantum circuits play a significant role in future quantum computing technology because they have many advantages over binary quantum circuits. Subtraction is considered as being one of the key arithmetic operations; hence, subtractors are very essential for the construction of various computational units of quantum computers and other complex computational systems. In this paper, we have proposed the realization of a quantum reversible ternary half-subtractor circuit using a generalized ternary gate, a ternary Toffoli gate, and a ternary C2NOT gate. Based on the realization of the ternary half-subtractor, we proposed the realization of a ternary full-subtractor.
Quantum processors are a central element of a quantum computer. Processors are responsible for performing the fundamental operations like addition, subtraction, etc. of any computer. This also involves the arithmetic unit and has a different configuration for the quantum computer than for a classical computer. Multiplication is essentially repeated addition and division is repeated subtraction. But for quantum computer other methodologies have to be used for arithmetic. In this paper a Quantum Full Adder/Subtractor Circuit, using the reversible Peres Gate, R3Gate and a NOT Gate, is proposed. So, the proposed design can be used for both modes, adder and subtractor on quantum operation. The authors have also compared proposed design with other designs reported, in terms of Gate count, Garbage bits, Quantum cost and Delay. The authors have achieved a 62.5% increment in delay and a low power computing reversible logic in which the computation is faster and energy efficient. Using IBM Qiskit, the authors have created and tested the circuit.
The ternary quantum circuit is very useful in arithmetic and logic operations. This circuit has several advantages as it reduces power dissipation, step time, etc. Adder circuit is the main block of various computing units and for several other complex computer designs. In this current paper, we have used generalized ternary gate (GTG) and reversible gates for the synthesis of reversible half adder and a full adder circuits. The presented designs offer reduced constant inputs and less quantum cost, compared to existing designs. Our proposed design allows a reduction of 40% of the cost and 25% of the number of gates used.