Abstract This study proposes and construct a primitive quantum arithmetic logic unit (qALU) based on the quantum Fourier transform (QFT). The qALU is capable of performing arithmetic ADD (addition) and logic NAND gate operations. It designs a scalable quantum circuit and presents the circuits for driving ADD and NAND operations on two‐input and four‐input quantum channels, respectively. By comparing the required number of quantum gates for serial and parallel architectures in executing arithmetic addition, it evaluates the performance. It also execute the proposed quantum Fourier transform‐based qALU design on real quantum processor hardware provided by IBM. The results demonstrate that the proposed circuit can perform arithmetic and logic operations with a high success rate. Furthermore, it discusses in detail the potential implementations of the qALU circuit in the field of computer science, highlighting the possibility of constructing a soft‐core processor on a quantum processing unit.
Abstract This study proposes and construct a primitive quantum arithmetic logic unit (qALU) based on the quantum Fourier transform (QFT). The qALU is capable of performing arithmetic ADD (addition) and logic NAND gate operations. It designs a scalable quantum circuit and presents the circuits for driving ADD and NAND operations on two‐input and four‐input quantum channels, respectively. By comparing the required number of quantum gates for serial and parallel architectures in executing arithmetic addition, it evaluates the performance. It also execute the proposed quantum Fourier transform‐based qALU design on real quantum processor hardware provided by IBM. The results demonstrate that the proposed circuit can perform arithmetic and logic operations with a high success rate. Furthermore, it discusses in detail the potential implementations of the qALU circuit in the field of computer science, highlighting the possibility of constructing a soft‐core processor on a quantum processing unit.
Quantum arithmetic logic units (QALUs) constitute a fundamental component of quantum computing. However, the implementation of QALUs on near-term quantum computers remains a substantial challenge, largely due to the limited connectivity of qubits. In this paper, we propose feasible QALUs, including quantum binary adders, subtractors, multipliers, and dividers, which are designed for near-term quantum computers with qubits arranged in two-dimensional arrays. Additionally, we introduce a feasible quantum arithmetic operation to compute the two's complement representation of signed integers. The proposed QALUs utilize only Pauli-X gates, CNOT gates, and CX (CSX) gates, and all two-qubit gates are operated between nearest neighbor qubits. Our work demonstrates a viable implementation of QALUs on near-term quantum computers, advancing towards scalable and resource-efficient quantum arithmetic operations.
Abstract Quantum arithmetic logic units (QALUs) are essential building blocks for quantum computation, yet their realization on near-term hardware is hindered by restricted qubit connectivity. Here we present hardware-efficient quantum arithmetic logic units (QALUs), including quantum adders, subtractors, multipliers, and dividers, for quantum computers with square lattice architectures. Our constructions rely solely on Pauli-X, CNOT, and controlled- X (CSX) gates, with all two-qubit operations confined to nearest-neitablghbor qubits. In addition, we introduce the quantum algorithm to obtain the two’s-complement representation of signed integers. These results demonstrate a scalable and hardware-efficient implementation of QALUs on square-grid quantum hardware, paving the way for more complex quantum algorithms on realistic devices.
This article demonstrates a quantum calculator by experimentally simulating and performing basic arithmetic operations, namely addition, subtraction, multiplication, division on real quantum devices using the IBM Quantum Experience (IBM QE) platform. Two addition algorithms are considered, the classical version, using the Toffoli gate, and using the quantum Fourier transform (QFT). In particular summation with QFT saves memory and time. The task of the work is to build a quantum circuit that performs arithmetic operations between the binary representation of two integers. We then propose a quantum algorithm for converting decimal to binary. This method also allows for massive parallelization during its execution. The addition, subtraction, multiplication, and division functions based on QFT have been improved with some changes. The proposed operations are compared with the closest quantum arithmetic operations. Therefore, we can implement a practical quantum calculator by performing operations on a real quantum computer. The circuits are defined as a kind of quantum adder using a quantum Fourier transform, implemented in Qiskit and demonstrated on one or two copies.
In this work, we develop quantum reversible counterparts of the logical AND, NAND, OR, NOR, and XOR gates within a single architectural template: a quantum Fourier transform (QFT)–based adder that emulates a digital half‐adder by computing the sum and carry of two input bits. Each member of the gate family is obtained from the same adder by inserting only X and SWAP gates as pre‐ and postprocessing steps, with the required Boolean identities supplied by De Morgan’s laws. We prove that every proposed circuit is unitary prior to readout, so the input data remain recoverable from the output state. The construction generalizes to N ‐input gates through an in‐place population‐count (Hamming‐weight) register, and we derive explicitly that the resulting qubit requirement is N + log 2 N , compared with the 2 N − 1 qubits of the standard Toffoli‐ladder synthesis; the derivation is validated by exhaustive simulation for N ≤ 8. We provide a comprehensive resource analysis‐qubit count, gate count, circuit depth, CX count, T count, transpiled depth, and success probability‐against Toffoli‐, CNOT‐, and X‐gate‐based reversible circuits as well as three multicontrolled‐NOT decompositions with different ancilla‐depth trade‐offs. The analysis shows that the qubit saving is obtained at the price of a larger two‐qubit‐gate count, and identifies the regimes in which the QFT‐based design is advantageous. All two‐input gates and a four‐input NAND instance are executed for every input combination on IBM quantum hardware and on a calibrated noise‐model simulator, and the measured outputs consistently reproduce the corresponding truth tables, with hardware success probabilities of 0.97–0.99 for the two‐input gates and 0.88–0.93 for the four‐input NAND.
Quantum computing is a transformative technology providing exponential speedup over classical computing for specific computational problems. At the foundation of computing lies arithmetic, with addition as a fundamental operation for subtraction, multiplication, division, and other operations. In this paper, we evaluate the performance of quantum arithmetic circuits – including half adders, full adders, Toffoli-based adders, Quantum Fourier Transform (QFT)-based adders, and quantum comparators – on IBM’s Eagle Processor, a 127-qubit superconducting Quantum Processing Unit (QPU) accessible through the IBM Quantum cloud platform. These circuits are implemented using IBM Qiskit and tested on both ideal and noisy simulators to validate their functionality before execution on quantum hardware. Experimental results show that the probabilities of accurate computations are notably low, even for smaller input sizes, due to hardware imperfections such as shorter qubit coherence times and limited qubit stability. A comparative analysis of Toffoli-based and QFT-based adders demonstrates that Toffoli-based adders have higher accuracy, making them more suitable for precise quantum arithmetic operations. These findings highlight the significant impact of quantum hardware imperfections on the reliability of arithmetic operations.
In this research, we create a scalable version of the quantum Fourier transform-based arithmetic circuit to perform addition and subtraction operations on N n-bit unsigned integers encoded in quantum registers, and it is compatible with d-level quantum sources, called qudits. We present qubit- and ququart-based multi-input QFT adders, and we compare and discuss potential benefits such as circuit simplicity and noise sensitivity. The results show that a ququart-based system significantly reduces gate count and improves computational efficiency compared to qubit-based systems. Overall, the findings presented in this study represent a promising step forward in the development of efficient quantum arithmetic circuits, particularly for multi-input operations, with clear advantages for ququart-based systems in reducing gate count, decoherence, and circuit complexity.