Resource‐Efficient Quantum Circuit Design for Reversible Logic Implementation

Abstract

In this work, we develop quantum reversible counterparts of the logical AND, NAND, OR, NOR, and XOR gates within a single architectural template: a quantum Fourier transform (QFT)–based adder that emulates a digital half‐adder by computing the sum and carry of two input bits. Each member of the gate family is obtained from the same adder by inserting only X and SWAP gates as pre‐ and postprocessing steps, with the required Boolean identities supplied by De Morgan’s laws. We prove that every proposed circuit is unitary prior to readout, so the input data remain recoverable from the output state. The construction generalizes to N ‐input gates through an in‐place population‐count (Hamming‐weight) register, and we derive explicitly that the resulting qubit requirement is N + log 2 N , compared with the 2 N − 1 qubits of the standard Toffoli‐ladder synthesis; the derivation is validated by exhaustive simulation for N ≤ 8. We provide a comprehensive resource analysis‐qubit count, gate count, circuit depth, CX count, T count, transpiled depth, and success probability‐against Toffoli‐, CNOT‐, and X‐gate‐based reversible circuits as well as three multicontrolled‐NOT decompositions with different ancilla‐depth trade‐offs. The analysis shows that the qubit saving is obtained at the price of a larger two‐qubit‐gate count, and identifies the regimes in which the QFT‐based design is advantageous. All two‐input gates and a four‐input NAND instance are executed for every input combination on IBM quantum hardware and on a calibrated noise‐model simulator, and the measured outputs consistently reproduce the corresponding truth tables, with hardware success probabilities of 0.97–0.99 for the two‐input gates and 0.88–0.93 for the four‐input NAND.